perf_counter: x86: More accurate counter update
Take the counter width into account instead of assuming 32 bits. In particular Nehalem has 44 bit wide counters, and all arithmetics should happen on a 44-bit signed integer basis. [ Impact: fix rare event imprecision, warning message on Nehalem ] Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -138,7 +138,9 @@ static u64
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x86_perf_counter_update(struct perf_counter *counter,
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x86_perf_counter_update(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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struct hw_perf_counter *hwc, int idx)
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{
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{
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u64 prev_raw_count, new_raw_count, delta;
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int shift = 64 - x86_pmu.counter_bits;
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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/*
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/*
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* Careful: an NMI might modify the previous counter value.
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* Careful: an NMI might modify the previous counter value.
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@ -161,9 +163,10 @@ again:
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* (counter-)time and add that to the generic counter.
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* (counter-)time and add that to the generic counter.
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*
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*
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* Careful, not all hw sign-extends above the physical width
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* Careful, not all hw sign-extends above the physical width
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* of the count, so we do that by clipping the delta to 32 bits:
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* of the count.
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*/
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*/
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delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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atomic64_add(delta, &counter->count);
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atomic64_add(delta, &counter->count);
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atomic64_sub(delta, &hwc->period_left);
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atomic64_sub(delta, &hwc->period_left);
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