ARM: dts: imx7s: add snvs rtc clock
Add i.MX7 SNVS RTC clock. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
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value type: <u32>
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value type: <u32>
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Definition: LP register offset. default it is 0x34.
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Definition: LP register offset. default it is 0x34.
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- clocks
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Usage: optional, required if SNVS LP RTC requires explicit
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enablement of clocks
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Value type: <prop_encoded-array>
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Definition: a clock specifier describing the clock required for
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enabling and disabling SNVS LP RTC.
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- clock-names
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Usage: optional, required if SNVS LP RTC requires explicit
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enablement of clocks
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Value type: <string>
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Definition: clock name string should be "snvs-rtc".
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EXAMPLE
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EXAMPLE
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sec_mon_rtc_lp@1 {
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sec_mon_rtc_lp@1 {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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interrupts = <93 2>;
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interrupts = <93 2>;
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regmap = <&snvs>;
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regmap = <&snvs>;
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offset = <0x34>;
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offset = <0x34>;
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clocks = <&clks IMX7D_SNVS_CLK>;
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clock-names = "snvs-rtc";
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};
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};
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=====================================================================
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=====================================================================
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@ -543,6 +558,8 @@ FULL EXAMPLE
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regmap = <&sec_mon>;
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regmap = <&sec_mon>;
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offset = <0x34>;
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offset = <0x34>;
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interrupts = <93 2>;
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interrupts = <93 2>;
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clocks = <&clks IMX7D_SNVS_CLK>;
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clock-names = "snvs-rtc";
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};
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};
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snvs-pwrkey@020cc000 {
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snvs-pwrkey@020cc000 {
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@ -551,6 +551,8 @@
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offset = <0x34>;
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_SNVS_CLK>;
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clock-names = "snvs-rtc";
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};
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};
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snvs_poweroff: snvs-poweroff {
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snvs_poweroff: snvs-poweroff {
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