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MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports

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The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.

The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Vladimir Oltean 2021-08-19 20:04:16 +03:00 committed by Thomas Bogendoerfer
parent 0181f6f19c
commit eba54cbb92
2 changed files with 8 additions and 0 deletions
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4
arch/mips/boot/dts/mscc/ocelot_pcb120.dts
View File

@ -71,21 +71,25 @@
&port0 { &port0 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "internal";
}; };
&port1 { &port1 {
status = "okay"; status = "okay";
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-mode = "internal";
}; };
&port2 { &port2 {
status = "okay"; status = "okay";
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-mode = "internal";
}; };
&port3 { &port3 {
status = "okay"; status = "okay";
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-mode = "internal";
}; };
&port4 { &port4 {

4
arch/mips/boot/dts/mscc/ocelot_pcb123.dts
View File

@ -49,19 +49,23 @@
&port0 { &port0 {
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "internal";
}; };
&port1 { &port1 {
status = "okay"; status = "okay";
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-mode = "internal";
}; };
&port2 { &port2 {
status = "okay"; status = "okay";
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-mode = "internal";
}; };
&port3 { &port3 {
status = "okay"; status = "okay";
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-mode = "internal";
}; };