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dt-bindings: memory: ti-emif: add edac support under emif

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Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
this in the DT binding. Also, add interrupts property as a required
property for the emif controller, as all revisions of the emif IP contain
interrupt support; this might remain unused by the kernel driver though.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
This commit is contained in:
Tero Kristo 2018-03-05 16:18:49 -08:00 committed by Santosh Shilimkar
parent 5a3a03905a
commit eae3c955bb
1 changed files with 12 additions and 1 deletions
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13
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
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@ -3,7 +3,9 @@
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.
of the EMIF IP and memory parts attached to it. Certain revisions
of the EMIF controller also contain optional ECC support, which
corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
@ -11,6 +13,8 @@ Required properties:
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
"ti,emif-dra7xx"
"ti,emif-keystone"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@ -22,6 +26,7 @@ Required properties:
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
- interrupts : interrupt used by the controller
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
@ -71,3 +76,9 @@ emif: emif@4c000000 {
sram = <&pm_sram_code
&pm_sram_data>;
};
emif1: emif@4c000000 {
compatible = "ti,emif-dra7xx";
reg = <0x4c000000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};