forked from Minki/linux
sky2: reorganize chip revision features
This patch should cause no functional changes in driver behaviour. There are (too) many revisions of the Yukon 2 chip now. Instead of adding more conditionals based on chip revision; rerganize into a set of feature flags so adding new versions is less problematic. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
c99210b50f
commit
ea76e63598
@ -217,8 +217,7 @@ static void sky2_power_on(struct sky2_hw *hw)
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else
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sky2_write8(hw, B2_Y2_CLK_GATE, 0);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
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hw->chip_id == CHIP_ID_YUKON_EX) {
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if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
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u32 reg;
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sky2_pci_write32(hw, PCI_DEV_REG3, 0);
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@ -311,10 +310,8 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
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if (sky2->autoneg == AUTONEG_ENABLE
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&& !(hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX)) {
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if (sky2->autoneg == AUTONEG_ENABLE &&
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!(hw->flags & SKY2_HW_NEWER_PHY)) {
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u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
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ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
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@ -346,9 +343,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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/* downshift on PHY 88E1112 and 88E1149 is changed */
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if (sky2->autoneg == AUTONEG_ENABLE
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&& (hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX)) {
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&& (hw->flags & SKY2_HW_NEWER_PHY)) {
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/* set downshift counter to 3x and enable downshift */
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ctrl &= ~PHY_M_PC_DSC_MSK;
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ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
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@ -364,7 +359,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
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gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
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/* special setup for PHY 88E1112 Fiber */
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if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
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if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
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pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
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@ -788,7 +783,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
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sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
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if (!(hw->flags & SKY2_HW_RAMBUFFER)) {
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sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
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sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
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@ -967,19 +962,15 @@ static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
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*/
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static void rx_set_checksum(struct sky2_port *sky2)
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{
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struct sky2_rx_le *le;
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struct sky2_rx_le *le = sky2_next_rx(sky2);
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if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
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le = sky2_next_rx(sky2);
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le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
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le->ctrl = 0;
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le->opcode = OP_TCPSTART | HW_OWNER;
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sky2_write32(sky2->hw,
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Q_ADDR(rxqaddr[sky2->port], Q_CSR),
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sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
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}
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le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
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le->ctrl = 0;
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le->opcode = OP_TCPSTART | HW_OWNER;
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sky2_write32(sky2->hw,
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Q_ADDR(rxqaddr[sky2->port], Q_CSR),
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sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
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}
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/*
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@ -1175,7 +1166,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
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sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
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rx_set_checksum(sky2);
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if (!(hw->flags & SKY2_HW_NEW_LE))
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rx_set_checksum(sky2);
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/* Space needed for frame data + headers rounded up */
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size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
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@ -1246,7 +1238,7 @@ static int sky2_up(struct net_device *dev)
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struct sky2_port *sky2 = netdev_priv(dev);
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struct sky2_hw *hw = sky2->hw;
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unsigned port = sky2->port;
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u32 ramsize, imask;
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u32 imask;
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int cap, err = -ENOMEM;
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struct net_device *otherdev = hw->dev[sky2->port^1];
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@ -1301,13 +1293,13 @@ static int sky2_up(struct net_device *dev)
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sky2_mac_init(hw, port);
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/* Register is number of 4K blocks on internal RAM buffer. */
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ramsize = sky2_read8(hw, B2_E_0) * 4;
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printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
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if (ramsize > 0) {
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if (hw->flags & SKY2_HW_RAMBUFFER) {
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/* Register is number of 4K blocks on internal RAM buffer. */
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u32 ramsize = sky2_read8(hw, B2_E_0) * 4;
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u32 rxspace;
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printk(KERN_DEBUG PFX "%s: ram buffer %dK\n", dev->name, ramsize);
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if (ramsize < 16)
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rxspace = ramsize / 2;
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else
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@ -1436,13 +1428,15 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
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/* Check for TCP Segmentation Offload */
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mss = skb_shinfo(skb)->gso_size;
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if (mss != 0) {
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if (hw->chip_id != CHIP_ID_YUKON_EX)
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if (!(hw->flags & SKY2_HW_NEW_LE))
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mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
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if (mss != sky2->tx_last_mss) {
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le = get_tx_le(sky2);
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le->addr = cpu_to_le32(mss);
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if (hw->chip_id == CHIP_ID_YUKON_EX)
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if (hw->flags & SKY2_HW_NEW_LE)
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le->opcode = OP_MSS | HW_OWNER;
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else
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le->opcode = OP_LRGLEN | HW_OWNER;
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@ -1468,8 +1462,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
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/* Handle TCP checksum offload */
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if (skb->ip_summed == CHECKSUM_PARTIAL) {
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/* On Yukon EX (some versions) encoding change. */
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if (hw->chip_id == CHIP_ID_YUKON_EX
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&& hw->chip_rev != CHIP_REV_YU_EX_B0)
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if (hw->flags & SKY2_HW_AUTO_TX_SUM)
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ctrl |= CALSUM; /* auto checksum */
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else {
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const unsigned offset = skb_transport_offset(skb);
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@ -1708,7 +1701,7 @@ static int sky2_down(struct net_device *dev)
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static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
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{
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if (!sky2_is_copper(hw))
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if (hw->flags & SKY2_HW_FIBRE_PHY)
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return SPEED_1000;
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if (hw->chip_id == CHIP_ID_YUKON_FE)
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@ -1753,9 +1746,7 @@ static void sky2_link_up(struct sky2_port *sky2)
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sky2_write8(hw, SK_REG(port, LNK_LED_REG),
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LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
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if (hw->chip_id == CHIP_ID_YUKON_XL
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|| hw->chip_id == CHIP_ID_YUKON_EC_U
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|| hw->chip_id == CHIP_ID_YUKON_EX) {
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if (hw->flags & SKY2_HW_NEWER_PHY) {
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u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
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@ -1847,7 +1838,7 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
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/* Since the pause result bits seem to in different positions on
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* different chips. look at registers.
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*/
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if (!sky2_is_copper(hw)) {
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if (hw->flags & SKY2_HW_FIBRE_PHY) {
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/* Shift for bits in fiber PHY */
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advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
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lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
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@ -2593,23 +2584,56 @@ static int __devinit sky2_init(struct sky2_hw *hw)
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sky2_write8(hw, B0_CTST, CS_RST_CLR);
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hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
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if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
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hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
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switch(hw->chip_id) {
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case CHIP_ID_YUKON_XL:
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hw->flags = SKY2_HW_GIGABIT
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| SKY2_HW_NEWER_PHY
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| SKY2_HW_RAMBUFFER;
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break;
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case CHIP_ID_YUKON_EC_U:
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hw->flags = SKY2_HW_GIGABIT
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| SKY2_HW_NEWER_PHY
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| SKY2_HW_ADV_POWER_CTL;
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break;
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case CHIP_ID_YUKON_EX:
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hw->flags = SKY2_HW_GIGABIT
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| SKY2_HW_NEWER_PHY
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| SKY2_HW_NEW_LE
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| SKY2_HW_ADV_POWER_CTL;
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/* New transmit checksum */
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if (hw->chip_rev != CHIP_REV_YU_EX_B0)
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hw->flags |= SKY2_HW_AUTO_TX_SUM;
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break;
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case CHIP_ID_YUKON_EC:
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/* This rev is really old, and requires untested workarounds */
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if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
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dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
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return -EOPNOTSUPP;
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}
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hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RAMBUFFER;
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break;
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case CHIP_ID_YUKON_FE:
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hw->flags = SKY2_HW_RAMBUFFER;
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break;
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default:
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dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
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hw->chip_id);
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return -EOPNOTSUPP;
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}
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hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
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/* This rev is really old, and requires untested workarounds */
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if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
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dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
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yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
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hw->chip_id, hw->chip_rev);
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return -EOPNOTSUPP;
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}
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hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
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if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
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hw->flags |= SKY2_HW_FIBRE_PHY;
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hw->ports = 1;
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t8 = sky2_read8(hw, B2_Y2_HW_RES);
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if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
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@ -2821,7 +2845,7 @@ static u32 sky2_supported_modes(const struct sky2_hw *hw)
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| SUPPORTED_100baseT_Full
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| SUPPORTED_Autoneg | SUPPORTED_TP;
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if (hw->chip_id != CHIP_ID_YUKON_FE)
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if (hw->flags & SKY2_HW_GIGABIT)
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modes |= SUPPORTED_1000baseT_Half
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| SUPPORTED_1000baseT_Full;
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return modes;
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@ -3851,7 +3875,7 @@ static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
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return IRQ_NONE;
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if (status & Y2_IS_IRQ_SW) {
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hw->msi = 1;
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hw->flags |= SKY2_HW_USE_MSI;
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wake_up(&hw->msi_wait);
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sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
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}
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@ -3879,9 +3903,9 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
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sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
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sky2_read8(hw, B0_CTST);
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wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
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wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
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if (!hw->msi) {
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if (!(hw->flags & SKY2_HW_USE_MSI)) {
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/* MSI test failed, go back to INTx mode */
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dev_info(&pdev->dev, "No interrupt generated using MSI, "
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"switching to INTx mode.\n");
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@ -4014,7 +4038,8 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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goto err_out_free_netdev;
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}
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err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
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err = request_irq(pdev->irq, sky2_intr,
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(hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
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dev->name, hw);
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if (err) {
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dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
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@ -4047,7 +4072,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
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return 0;
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err_out_unregister:
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if (hw->msi)
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if (hw->flags & SKY2_HW_USE_MSI)
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pci_disable_msi(pdev);
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unregister_netdev(dev);
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err_out_free_netdev:
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@ -4096,7 +4121,7 @@ static void __devexit sky2_remove(struct pci_dev *pdev)
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sky2_read8(hw, B0_CTST);
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free_irq(pdev->irq, hw);
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if (hw->msi)
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if (hw->flags & SKY2_HW_USE_MSI)
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pci_disable_msi(pdev);
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pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
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pci_release_regions(pdev);
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@ -2040,6 +2040,15 @@ struct sky2_hw {
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void __iomem *regs;
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struct pci_dev *pdev;
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struct net_device *dev[2];
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unsigned long flags;
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#define SKY2_HW_USE_MSI 0x00000001
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#define SKY2_HW_FIBRE_PHY 0x00000002
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#define SKY2_HW_GIGABIT 0x00000004
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#define SKY2_HW_NEWER_PHY 0x00000008
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#define SKY2_HW_RAMBUFFER 0x00000010 /* chip has RAM FIFO */
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#define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
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#define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
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#define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
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u8 chip_id;
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u8 chip_rev;
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@ -2053,13 +2062,12 @@ struct sky2_hw {
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struct timer_list watchdog_timer;
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struct work_struct restart_work;
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int msi;
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wait_queue_head_t msi_wait;
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};
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static inline int sky2_is_copper(const struct sky2_hw *hw)
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{
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return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P');
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return !(hw->flags & SKY2_HW_FIBRE_PHY);
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}
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/* Register accessor for memory mapped device */
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