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ASoC: qcom: qdsp6: q6prm: add new clocks

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Add support to new clocks that are added in Q6DSP as part of newer version
of LPASS support on SM8450 and SC8280XP.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220816170118.13470-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2022-08-16 18:01:18 +01:00 committed by Mark Brown
parent 43a70fb51b
commit ea15d3bd3c
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
3 changed files with 46 additions and 0 deletions
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18
include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
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@ -193,6 +193,24 @@
#define LPASS_CLK_ID_RX_CORE_MCLK 59 #define LPASS_CLK_ID_RX_CORE_MCLK 59
#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 #define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 #define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
/* Clock ID for MCLK for WSA2 core */
#define LPASS_CLK_ID_WSA2_CORE_MCLK 62
/* Clock ID for NPL MCLK for WSA2 core */
#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63
/* Clock ID for RX Core TX MCLK */
#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64
/* Clock ID for RX CORE TX 2X MCLK */
#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65
/* Clock ID for WSA core TX MCLK */
#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66
/* Clock ID for WSA core TX 2X MCLK */
#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67
/* Clock ID for WSA2 core TX MCLK */
#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68
/* Clock ID for WSA2 core TX 2X MCLK */
#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69
/* Clock ID for RX CORE MCLK2 2X MCLK */
#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70
#define LPASS_HW_AVTIMER_VOTE 101 #define LPASS_HW_AVTIMER_VOTE 101
#define LPASS_HW_MACRO_VOTE 102 #define LPASS_HW_MACRO_VOTE 102

9
sound/soc/qcom/qdsp6/q6prm-clocks.c
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@ -50,6 +50,15 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK), Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK), Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK), Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS, Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
"LPASS_HW_MACRO"), "LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC, Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,

19
sound/soc/qcom/qdsp6/q6prm.h
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@ -64,6 +64,25 @@
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e #define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f #define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
/* Clock ID for MCLK for WSA2 core */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310
/* Clock ID for NPL MCLK for WSA2 core */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311
/* Clock ID for RX Core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312
/* Clock ID for RX CORE TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313
/* Clock ID for WSA core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314
/* Clock ID for WSA core TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315
/* Clock ID for WSA2 core TX MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316
/* Clock ID for WSA2 core TX 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317
/* Clock ID for RX CORE MCLK2 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1 #define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0 #define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
#define Q6PRM_HW_CORE_ID_LPASS 1 #define Q6PRM_HW_CORE_ID_LPASS 1