Merge remote-tracking branch 'agust/next' into next
<< Switch mpc512x to the common clock framework and adapt mpc512x drivers to use the new clock driver. Old PPC_CLOCK code is removed entirely since there are no users any more. >>
This commit is contained in:
Benjamin Herrenschmidt
@@ -108,135 +108,170 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
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#endif /* CONFIG_PPC_MPC52xx */
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#ifdef CONFIG_PPC_MPC512x
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struct mpc512x_clockctl {
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u32 spmr; /* System PLL Mode Reg */
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u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
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u32 scfr1; /* System Clk Freq Reg 1 */
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u32 scfr2; /* System Clk Freq Reg 2 */
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u32 reserved;
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u32 bcr; /* Bread Crumb Reg */
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u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
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u32 spccr; /* SPDIF Clk Ctrl Reg */
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u32 cccr; /* CFM Clk Ctrl Reg */
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u32 dccr; /* DIU Clk Cnfg Reg */
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u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
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};
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static struct of_device_id mpc512x_clock_ids[] = {
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{ .compatible = "fsl,mpc5121-clock", },
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{}
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};
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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const char *clock_name, int *mscan_clksrc)
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const char *clock_source, int *mscan_clksrc)
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{
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struct mpc512x_clockctl __iomem *clockctl;
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struct device_node *np_clock;
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struct clk *sys_clk, *ref_clk;
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int plen, clockidx, clocksrc = -1;
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u32 sys_freq, val, clockdiv = 1, freq = 0;
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const u32 *pval;
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struct device_node *np;
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u32 clockdiv;
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enum {
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CLK_FROM_AUTO,
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CLK_FROM_IPS,
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CLK_FROM_SYS,
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CLK_FROM_REF,
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} clk_from;
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struct clk *clk_in, *clk_can;
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unsigned long freq_calc;
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struct mscan_priv *priv;
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struct clk *clk_ipg;
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np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
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if (!np_clock) {
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dev_err(&ofdev->dev, "couldn't find clock node\n");
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return 0;
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/* the caller passed in the clock source spec that was read from
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* the device tree, get the optional clock divider as well
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*/
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np = ofdev->dev.of_node;
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clockdiv = 1;
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of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
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dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
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clock_source ? clock_source : "<NULL>", clockdiv);
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/* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
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* get set, and the 'ips' clock is the input to the MSCAN
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* component
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*
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* for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
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* bit needs to get cleared, an optional clock-divider may have
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* been specified (the default value is 1), the appropriate
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* MSCAN related MCLK is the input to the MSCAN component
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*
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* in the absence of a clock-source spec, first an optimal clock
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* gets determined based on the 'sys' clock, if that fails the
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* 'ref' clock is used
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*/
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clk_from = CLK_FROM_AUTO;
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if (clock_source) {
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/* interpret the device tree's spec for the clock source */
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if (!strcmp(clock_source, "ip"))
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clk_from = CLK_FROM_IPS;
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else if (!strcmp(clock_source, "sys"))
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clk_from = CLK_FROM_SYS;
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else if (!strcmp(clock_source, "ref"))
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clk_from = CLK_FROM_REF;
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else
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goto err_invalid;
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dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
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}
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clockctl = of_iomap(np_clock, 0);
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if (!clockctl) {
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dev_err(&ofdev->dev, "couldn't map clock registers\n");
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goto exit_put;
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if (clk_from == CLK_FROM_AUTO) {
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/* no spec so far, try the 'sys' clock; round to the
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* next MHz and see if we can get a multiple of 16MHz
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*/
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dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
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clk_in = devm_clk_get(&ofdev->dev, "sys");
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if (IS_ERR(clk_in))
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goto err_notavail;
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freq_calc = clk_get_rate(clk_in);
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freq_calc += 499999;
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freq_calc /= 1000000;
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freq_calc *= 1000000;
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if ((freq_calc % 16000000) == 0) {
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clk_from = CLK_FROM_SYS;
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clockdiv = freq_calc / 16000000;
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dev_dbg(&ofdev->dev,
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"clk fit, sys[%lu] div[%d] freq[%lu]\n",
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freq_calc, clockdiv, freq_calc / clockdiv);
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}
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}
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if (clk_from == CLK_FROM_AUTO) {
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/* no spec so far, use the 'ref' clock */
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dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
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clk_in = devm_clk_get(&ofdev->dev, "ref");
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if (IS_ERR(clk_in))
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goto err_notavail;
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clk_from = CLK_FROM_REF;
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freq_calc = clk_get_rate(clk_in);
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dev_dbg(&ofdev->dev,
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"clk fit, ref[%lu] (no div) freq[%lu]\n",
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freq_calc, freq_calc);
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}
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/* Determine the MSCAN device index from the peripheral's
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* physical address. Register address offsets against the
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* IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
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/* select IPS or MCLK as the MSCAN input (returned to the caller),
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* setup the MCLK mux source and rate if applicable, apply the
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* optionally specified or derived above divider, and determine
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* the actual resulting clock rate to return to the caller
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*/
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pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
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BUG_ON(!pval || plen < sizeof(*pval));
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clockidx = (*pval & 0x80) ? 1 : 0;
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if (*pval & 0x2000)
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clockidx += 2;
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/*
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* Clock source and divider selection: 3 different clock sources
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* can be selected: "ip", "ref" or "sys". For the latter two, a
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* clock divider can be defined as well. If the clock source is
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* not specified by the device tree, we first try to find an
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* optimal CAN source clock based on the system clock. If that
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* is not posslible, the reference clock will be used.
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*/
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if (clock_name && !strcmp(clock_name, "ip")) {
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switch (clk_from) {
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case CLK_FROM_IPS:
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clk_can = devm_clk_get(&ofdev->dev, "ips");
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if (IS_ERR(clk_can))
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goto err_notavail;
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
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priv->clk_can = clk_can;
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freq_calc = clk_get_rate(clk_can);
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*mscan_clksrc = MSCAN_CLKSRC_IPS;
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freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
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} else {
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dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
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*mscan_clksrc, freq_calc);
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break;
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case CLK_FROM_SYS:
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case CLK_FROM_REF:
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clk_can = devm_clk_get(&ofdev->dev, "mclk");
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if (IS_ERR(clk_can))
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goto err_notavail;
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
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priv->clk_can = clk_can;
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if (clk_from == CLK_FROM_SYS)
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clk_in = devm_clk_get(&ofdev->dev, "sys");
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if (clk_from == CLK_FROM_REF)
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clk_in = devm_clk_get(&ofdev->dev, "ref");
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if (IS_ERR(clk_in))
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goto err_notavail;
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clk_set_parent(clk_can, clk_in);
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freq_calc = clk_get_rate(clk_in);
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freq_calc /= clockdiv;
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clk_set_rate(clk_can, freq_calc);
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freq_calc = clk_get_rate(clk_can);
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*mscan_clksrc = MSCAN_CLKSRC_BUS;
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pval = of_get_property(ofdev->dev.of_node,
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"fsl,mscan-clock-divider", &plen);
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if (pval && plen == sizeof(*pval))
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clockdiv = *pval;
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if (!clockdiv)
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clockdiv = 1;
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if (!clock_name || !strcmp(clock_name, "sys")) {
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sys_clk = devm_clk_get(&ofdev->dev, "sys_clk");
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if (IS_ERR(sys_clk)) {
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dev_err(&ofdev->dev, "couldn't get sys_clk\n");
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goto exit_unmap;
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}
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/* Get and round up/down sys clock rate */
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sys_freq = 1000000 *
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((clk_get_rate(sys_clk) + 499999) / 1000000);
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if (!clock_name) {
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/* A multiple of 16 MHz would be optimal */
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if ((sys_freq % 16000000) == 0) {
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clocksrc = 0;
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clockdiv = sys_freq / 16000000;
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freq = sys_freq / clockdiv;
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}
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} else {
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clocksrc = 0;
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freq = sys_freq / clockdiv;
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}
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}
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if (clocksrc < 0) {
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ref_clk = devm_clk_get(&ofdev->dev, "ref_clk");
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if (IS_ERR(ref_clk)) {
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dev_err(&ofdev->dev, "couldn't get ref_clk\n");
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goto exit_unmap;
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}
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clocksrc = 1;
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freq = clk_get_rate(ref_clk) / clockdiv;
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}
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dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
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*mscan_clksrc, freq_calc);
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break;
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default:
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goto err_invalid;
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}
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/* Disable clock */
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out_be32(&clockctl->mccr[clockidx], 0x0);
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if (clocksrc >= 0) {
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/* Set source and divider */
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val = (clocksrc << 14) | ((clockdiv - 1) << 17);
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out_be32(&clockctl->mccr[clockidx], val);
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/* Enable clock */
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out_be32(&clockctl->mccr[clockidx], val | 0x10000);
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}
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/* the above clk_can item is used for the bitrate, access to
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* the peripheral's register set needs the clk_ipg item
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*/
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clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
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if (IS_ERR(clk_ipg))
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goto err_notavail_ipg;
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if (clk_prepare_enable(clk_ipg))
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goto err_notavail_ipg;
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
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priv->clk_ipg = clk_ipg;
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/* Enable MSCAN clock domain */
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val = in_be32(&clockctl->sccr[1]);
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if (!(val & (1 << 25)))
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out_be32(&clockctl->sccr[1], val | (1 << 25));
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/* return the determined clock source rate */
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return freq_calc;
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dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
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*mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
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clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
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err_invalid:
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dev_err(&ofdev->dev, "invalid clock source specification\n");
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/* clock source rate could not get determined */
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return 0;
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exit_unmap:
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iounmap(clockctl);
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exit_put:
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of_node_put(np_clock);
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return freq;
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err_notavail:
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dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
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/* clock source rate could not get determined */
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return 0;
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err_notavail_ipg:
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dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
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/* clock source rate could not get determined */
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return 0;
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}
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static void mpc512x_can_put_clock(struct platform_device *ofdev)
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{
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struct mscan_priv *priv;
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priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
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if (priv->clk_ipg)
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clk_disable_unprepare(priv->clk_ipg);
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}
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#else /* !CONFIG_PPC_MPC512x */
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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@@ -244,6 +279,7 @@ static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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{
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return 0;
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}
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#define mpc512x_can_put_clock NULL
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#endif /* CONFIG_PPC_MPC512x */
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static const struct of_device_id mpc5xxx_can_table[];
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@@ -385,11 +421,13 @@ static int mpc5xxx_can_resume(struct platform_device *ofdev)
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static const struct mpc5xxx_can_data mpc5200_can_data = {
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.type = MSCAN_TYPE_MPC5200,
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.get_clock = mpc52xx_can_get_clock,
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/* .put_clock not applicable */
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};
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static const struct mpc5xxx_can_data mpc5121_can_data = {
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.type = MSCAN_TYPE_MPC5121,
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.get_clock = mpc512x_can_get_clock,
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.put_clock = mpc512x_can_put_clock,
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};
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static const struct of_device_id mpc5xxx_can_table[] = {
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