misc: Add Synopsys DesignWare xData IP driver
Add Synopsys DesignWare xData IP driver. This driver enables/disables the PCI traffic generator module pertain to the Synopsys DesignWare prototype. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Link: https://lore.kernel.org/r/daa1efe23850e77d6807dc3f371728fc0b7548b8.1617016509.git.gustavo.pimentel@synopsys.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gustavo Pimentel
Greg Kroah-Hartman
parent
b2192cfeba
commit
e8a30eef6e
@ -402,6 +402,16 @@ config SRAM
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config SRAM_EXEC
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bool
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config DW_XDATA_PCIE
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depends on PCI
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tristate "Synopsys DesignWare xData PCIe driver"
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help
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This driver allows controlling Synopsys DesignWare PCIe traffic
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generator IP also known as xData, present in Synopsys DesignWare
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PCIe Endpoint prototype.
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If unsure, say N.
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config PCI_ENDPOINT_TEST
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depends on PCI
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select CRC32
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@ -47,6 +47,7 @@ obj-$(CONFIG_SRAM_EXEC) += sram-exec.o
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obj-$(CONFIG_GENWQE) += genwqe/
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obj-$(CONFIG_ECHO) += echo/
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obj-$(CONFIG_CXL_BASE) += cxl/
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obj-$(CONFIG_DW_XDATA_PCIE) += dw-xdata-pcie.o
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obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
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obj-$(CONFIG_OCXL) += ocxl/
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obj-$(CONFIG_BCM_VK) += bcm-vk/
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420
drivers/misc/dw-xdata-pcie.c
Normal file
420
drivers/misc/dw-xdata-pcie.c
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@ -0,0 +1,420 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare xData driver
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#include <linux/miscdevice.h>
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#include <linux/bitfield.h>
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#include <linux/pci-epf.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
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#define DW_XDATA_EP_MEM_OFFSET 0x8000000
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static DEFINE_IDA(xdata_ida);
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#define STATUS_DONE BIT(0)
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#define CONTROL_DOORBELL BIT(0)
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#define CONTROL_IS_WRITE BIT(1)
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#define CONTROL_LENGTH(a) FIELD_PREP(GENMASK(13, 2), a)
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#define CONTROL_PATTERN_INC BIT(16)
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#define CONTROL_NO_ADDR_INC BIT(18)
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#define XPERF_CONTROL_ENABLE BIT(5)
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#define BURST_REPEAT BIT(31)
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#define BURST_VALUE 0x1001
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#define PATTERN_VALUE 0x0
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struct dw_xdata_regs {
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u32 addr_lsb; /* 0x000 */
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u32 addr_msb; /* 0x004 */
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u32 burst_cnt; /* 0x008 */
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u32 control; /* 0x00c */
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u32 pattern; /* 0x010 */
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u32 status; /* 0x014 */
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u32 RAM_addr; /* 0x018 */
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u32 RAM_port; /* 0x01c */
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u32 _reserved0[14]; /* 0x020..0x054 */
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u32 perf_control; /* 0x058 */
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u32 _reserved1[41]; /* 0x05c..0x0fc */
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u32 wr_cnt_lsb; /* 0x100 */
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u32 wr_cnt_msb; /* 0x104 */
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u32 rd_cnt_lsb; /* 0x108 */
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u32 rd_cnt_msb; /* 0x10c */
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} __packed;
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struct dw_xdata_region {
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phys_addr_t paddr; /* physical address */
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void __iomem *vaddr; /* virtual address */
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};
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struct dw_xdata {
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struct dw_xdata_region rg_region; /* registers */
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size_t max_wr_len; /* max wr xfer len */
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size_t max_rd_len; /* max rd xfer len */
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struct mutex mutex;
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struct pci_dev *pdev;
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struct miscdevice misc_dev;
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};
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static inline struct dw_xdata_regs __iomem *__dw_regs(struct dw_xdata *dw)
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{
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return dw->rg_region.vaddr;
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}
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static void dw_xdata_stop(struct dw_xdata *dw)
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{
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u32 burst;
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mutex_lock(&dw->mutex);
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burst = readl(&(__dw_regs(dw)->burst_cnt));
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if (burst & BURST_REPEAT) {
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burst &= ~(u32)BURST_REPEAT;
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writel(burst, &(__dw_regs(dw)->burst_cnt));
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}
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mutex_unlock(&dw->mutex);
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}
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static void dw_xdata_start(struct dw_xdata *dw, bool write)
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{
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struct device *dev = &dw->pdev->dev;
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u32 control, status;
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/* Stop first if xfer in progress */
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dw_xdata_stop(dw);
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mutex_lock(&dw->mutex);
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/* Clear status register */
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writel(0x0, &(__dw_regs(dw)->status));
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/* Burst count register set for continuous until stopped */
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writel(BURST_REPEAT | BURST_VALUE, &(__dw_regs(dw)->burst_cnt));
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/* Pattern register */
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writel(PATTERN_VALUE, &(__dw_regs(dw)->pattern));
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/* Control register */
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control = CONTROL_DOORBELL | CONTROL_PATTERN_INC | CONTROL_NO_ADDR_INC;
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if (write) {
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control |= CONTROL_IS_WRITE;
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control |= CONTROL_LENGTH(dw->max_wr_len);
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} else {
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control |= CONTROL_LENGTH(dw->max_rd_len);
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}
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writel(control, &(__dw_regs(dw)->control));
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/*
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* The xData HW block needs about 100 ms to initiate the traffic
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* generation according this HW block datasheet.
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*/
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usleep_range(100, 150);
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status = readl(&(__dw_regs(dw)->status));
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mutex_unlock(&dw->mutex);
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if (!(status & STATUS_DONE))
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dev_dbg(dev, "xData: started %s direction\n",
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write ? "write" : "read");
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}
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static void dw_xdata_perf_meas(struct dw_xdata *dw, u64 *data, bool write)
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{
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if (write) {
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*data = readl(&(__dw_regs(dw)->wr_cnt_msb));
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*data <<= 32;
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*data |= readl(&(__dw_regs(dw)->wr_cnt_lsb));
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} else {
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*data = readl(&(__dw_regs(dw)->rd_cnt_msb));
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*data <<= 32;
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*data |= readl(&(__dw_regs(dw)->rd_cnt_lsb));
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}
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}
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static u64 dw_xdata_perf_diff(u64 *m1, u64 *m2, u64 time)
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{
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u64 rate = (*m1 - *m2);
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rate *= (1000 * 1000 * 1000);
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rate >>= 20;
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rate = DIV_ROUND_CLOSEST_ULL(rate, time);
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return rate;
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}
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static void dw_xdata_perf(struct dw_xdata *dw, u64 *rate, bool write)
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{
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struct device *dev = &dw->pdev->dev;
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u64 data[2], time[2], diff;
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mutex_lock(&dw->mutex);
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/* First acquisition of current count frames */
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writel(0x0, &(__dw_regs(dw)->perf_control));
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dw_xdata_perf_meas(dw, &data[0], write);
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time[0] = jiffies;
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writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
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/*
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* Wait 100ms between the 1st count frame acquisition and the 2nd
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* count frame acquisition, in order to calculate the speed later
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*/
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mdelay(100);
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/* Second acquisition of current count frames */
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writel(0x0, &(__dw_regs(dw)->perf_control));
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dw_xdata_perf_meas(dw, &data[1], write);
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time[1] = jiffies;
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writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
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/*
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* Speed calculation
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*
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* rate = (2nd count frames - 1st count frames) / (time elapsed)
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*/
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diff = jiffies_to_nsecs(time[1] - time[0]);
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*rate = dw_xdata_perf_diff(&data[1], &data[0], diff);
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mutex_unlock(&dw->mutex);
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dev_dbg(dev, "xData: time=%llu us, %s=%llu MB/s\n",
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diff, write ? "write" : "read", *rate);
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}
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static struct dw_xdata *misc_dev_to_dw(struct miscdevice *misc_dev)
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{
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return container_of(misc_dev, struct dw_xdata, misc_dev);
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}
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static ssize_t write_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct miscdevice *misc_dev = dev_get_drvdata(dev);
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struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
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u64 rate;
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dw_xdata_perf(dw, &rate, true);
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return sysfs_emit(buf, "%llu\n", rate);
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}
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static ssize_t write_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t size)
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{
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struct miscdevice *misc_dev = dev_get_drvdata(dev);
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struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
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bool enabled;
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int ret;
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ret = kstrtobool(buf, &enabled);
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if (ret < 0)
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return ret;
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if (enabled) {
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dev_dbg(dev, "xData: requested write transfer\n");
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dw_xdata_start(dw, true);
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} else {
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dev_dbg(dev, "xData: requested stop transfer\n");
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dw_xdata_stop(dw);
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}
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return size;
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}
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static DEVICE_ATTR_RW(write);
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static ssize_t read_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct miscdevice *misc_dev = dev_get_drvdata(dev);
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struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
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u64 rate;
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dw_xdata_perf(dw, &rate, false);
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return sysfs_emit(buf, "%llu\n", rate);
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}
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static ssize_t read_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t size)
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{
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struct miscdevice *misc_dev = dev_get_drvdata(dev);
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struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
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bool enabled;
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int ret;
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ret = kstrtobool(buf, &enabled);
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if (ret < 0)
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return ret;
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if (enabled) {
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dev_dbg(dev, "xData: requested read transfer\n");
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dw_xdata_start(dw, false);
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} else {
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dev_dbg(dev, "xData: requested stop transfer\n");
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dw_xdata_stop(dw);
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}
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return size;
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}
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static DEVICE_ATTR_RW(read);
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static struct attribute *xdata_attrs[] = {
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&dev_attr_write.attr,
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&dev_attr_read.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(xdata);
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static int dw_xdata_pcie_probe(struct pci_dev *pdev,
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const struct pci_device_id *pid)
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{
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struct device *dev = &pdev->dev;
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struct dw_xdata *dw;
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char name[24];
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u64 addr;
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int err;
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int id;
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/* Enable PCI device */
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err = pcim_enable_device(pdev);
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if (err) {
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dev_err(dev, "enabling device failed\n");
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return err;
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}
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/* Mapping PCI BAR regions */
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err = pcim_iomap_regions(pdev, BIT(BAR_0), pci_name(pdev));
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if (err) {
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dev_err(dev, "xData BAR I/O remapping failed\n");
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return err;
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}
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pci_set_master(pdev);
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/* Allocate memory */
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dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
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if (!dw)
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return -ENOMEM;
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/* Data structure initialization */
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mutex_init(&dw->mutex);
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dw->rg_region.vaddr = pcim_iomap_table(pdev)[BAR_0];
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if (!dw->rg_region.vaddr)
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return -ENOMEM;
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dw->rg_region.paddr = pdev->resource[BAR_0].start;
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dw->max_wr_len = pcie_get_mps(pdev);
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dw->max_wr_len >>= 2;
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dw->max_rd_len = pcie_get_readrq(pdev);
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dw->max_rd_len >>= 2;
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dw->pdev = pdev;
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id = ida_simple_get(&xdata_ida, 0, 0, GFP_KERNEL);
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if (id < 0) {
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dev_err(dev, "xData: unable to get id\n");
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return id;
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}
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snprintf(name, sizeof(name), DW_XDATA_DRIVER_NAME ".%d", id);
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dw->misc_dev.name = kstrdup(name, GFP_KERNEL);
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if (!dw->misc_dev.name) {
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err = -ENOMEM;
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goto err_ida_remove;
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}
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dw->misc_dev.minor = MISC_DYNAMIC_MINOR;
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dw->misc_dev.parent = dev;
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dw->misc_dev.groups = xdata_groups;
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writel(0x0, &(__dw_regs(dw)->RAM_addr));
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writel(0x0, &(__dw_regs(dw)->RAM_port));
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addr = dw->rg_region.paddr + DW_XDATA_EP_MEM_OFFSET;
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writel(lower_32_bits(addr), &(__dw_regs(dw)->addr_lsb));
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writel(upper_32_bits(addr), &(__dw_regs(dw)->addr_msb));
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dev_dbg(dev, "xData: target address = 0x%.16llx\n", addr);
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dev_dbg(dev, "xData: wr_len = %zu, rd_len = %zu\n",
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dw->max_wr_len * 4, dw->max_rd_len * 4);
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/* Saving data structure reference */
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pci_set_drvdata(pdev, dw);
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/* Register misc device */
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err = misc_register(&dw->misc_dev);
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if (err) {
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dev_err(dev, "xData: failed to register device\n");
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goto err_kfree_name;
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}
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return 0;
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err_kfree_name:
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kfree(dw->misc_dev.name);
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err_ida_remove:
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ida_simple_remove(&xdata_ida, id);
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return err;
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}
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static void dw_xdata_pcie_remove(struct pci_dev *pdev)
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{
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struct dw_xdata *dw = pci_get_drvdata(pdev);
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int id;
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if (sscanf(dw->misc_dev.name, DW_XDATA_DRIVER_NAME ".%d", &id) != 1)
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return;
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if (id < 0)
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return;
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dw_xdata_stop(dw);
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misc_deregister(&dw->misc_dev);
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kfree(dw->misc_dev.name);
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ida_simple_remove(&xdata_ida, id);
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}
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static const struct pci_device_id dw_xdata_pcie_id_table[] = {
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{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, dw_xdata_pcie_id_table);
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static struct pci_driver dw_xdata_pcie_driver = {
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.name = DW_XDATA_DRIVER_NAME,
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.id_table = dw_xdata_pcie_id_table,
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.probe = dw_xdata_pcie_probe,
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.remove = dw_xdata_pcie_remove,
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};
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module_pci_driver(dw_xdata_pcie_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Synopsys DesignWare xData PCIe driver");
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MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
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