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drm/amdgpu: enable lbpw on raven

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Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2017-05-26 14:40:36 +08:00 committed by Alex Deucher
parent ba7bb6658e
commit e8835e0e43
3 changed files with 23 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@ -111,6 +111,7 @@ extern int amdgpu_pos_buf_per_se;
extern int amdgpu_cntl_sb_buf_per_se;
extern int amdgpu_param_buf_per_se;
extern int amdgpu_job_hang_limit;
extern int amdgpu_lbpw;
#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000

3
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -113,6 +113,7 @@ int amdgpu_pos_buf_per_se = 0;
int amdgpu_cntl_sb_buf_per_se = 0;
int amdgpu_param_buf_per_se = 0;
int amdgpu_job_hang_limit = 0;
int amdgpu_lbpw = -1;
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@ -238,6 +239,8 @@ module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(lbpw, amdgpu_lbpw, int, 0444);
static const struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_SI

19
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -683,6 +683,18 @@ static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
mutex_unlock(&adev->grbm_idx_mutex);
}
static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
{
uint32_t data = 0;
data = RREG32_SOC15(GC, 0, mmRLC_LB_CNTL);
if (enable)
data |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
else
data &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
}
static void rv_init_cp_jump_table(struct amdgpu_device *adev)
{
const __le32 *fw_data;
@ -2229,6 +2241,13 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
return r;
}
if (adev->asic_type == CHIP_RAVEN) {
if (amdgpu_lbpw != 0)
gfx_v9_0_enable_lbpw(adev, true);
else
gfx_v9_0_enable_lbpw(adev, false);
}
gfx_v9_0_rlc_start(adev);
return 0;