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drm/amd/display: fix dcn fe reset memory access error

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2017-07-28 14:16:13 -04:00
committed by Alex Deucher
parent f669089aa1
commit e75504b129
1 changed files with 4 additions and 3 deletions
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7
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
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@@ -853,8 +853,9 @@ static void plane_atomic_disable(struct core_dc *dc,
struct dce_hwseq *hws = dc->hwseq; struct dce_hwseq *hws = dc->hwseq;
struct mem_input *mi = dc->res_pool->mis[fe_idx]; struct mem_input *mi = dc->res_pool->mis[fe_idx];
struct mpc *mpc = dc->res_pool->mpc; struct mpc *mpc = dc->res_pool->mpc;
int opp_id = mi->opp_id;
if (mi->opp_id == 0xf) if (opp_id == 0xf)
return; return;
mpc->funcs->wait_for_idle(mpc, mi->mpcc_id); mpc->funcs->wait_for_idle(mpc, mi->mpcc_id);
@@ -876,8 +877,8 @@ static void plane_atomic_disable(struct core_dc *dc,
REG_UPDATE(DPP_CONTROL[fe_idx], REG_UPDATE(DPP_CONTROL[fe_idx],
DPP_CLOCK_ENABLE, 0); DPP_CLOCK_ENABLE, 0);
if (dc->res_pool->opps[mi->opp_id]->mpc_tree.num_pipes == 0) if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
REG_UPDATE(OPP_PIPE_CONTROL[mi->opp_id], REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
OPP_PIPE_CLOCK_EN, 0); OPP_PIPE_CLOCK_EN, 0);
if (dc->public.debug.sanity_checks) if (dc->public.debug.sanity_checks)