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drm/nouveau/pm: switch to instanced constructor

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 16:07:49 +10:00
parent ee532a8d0e
commit e73d371a73
18 changed files with 83 additions and 86 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_pm *pm;
struct nvkm_engine *sec;
struct nvkm_sec2 *sec2;
struct nvkm_sw *sw;
@ -106,7 +105,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -41,4 +41,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld)
NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 3)
NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_PM , struct nvkm_pm , pm)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

18
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
View File

@ -17,13 +17,13 @@ struct nvkm_pm {
u32 sequence;
};
int nv40_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int nv50_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int g84_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gt200_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gt215_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf100_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf108_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gf117_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int gk104_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
int nv40_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int nv50_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int g84_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gt200_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gt215_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gf100_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gf108_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gf117_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
int gk104_pm_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pm **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_PM ] = "pm",
[NVKM_ENGINE_SEC ] = "sec",
[NVKM_ENGINE_SEC2 ] = "sec2",
[NVKM_ENGINE_SW ] = "sw",

87
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -491,7 +491,7 @@ nv40_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -517,7 +517,7 @@ nv41_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -543,7 +543,7 @@ nv42_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -569,7 +569,7 @@ nv43_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv40_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -595,7 +595,7 @@ nv44_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -621,7 +621,7 @@ nv45_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -647,7 +647,7 @@ nv46_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -673,7 +673,7 @@ nv47_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -699,7 +699,7 @@ nv49_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -725,7 +725,7 @@ nv4a_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -751,7 +751,7 @@ nv4b_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv40_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -777,7 +777,7 @@ nv4c_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -803,7 +803,7 @@ nv4e_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -832,7 +832,7 @@ nv50_chipset = {
.fifo = { 0x00000001, nv50_fifo_new },
.gr = { 0x00000001, nv50_gr_new },
.mpeg = { 0x00000001, nv50_mpeg_new },
.pm = nv50_pm_new,
.pm = { 0x00000001, nv50_pm_new },
.sw = nv50_sw_new,
};
@ -858,7 +858,7 @@ nv63_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -884,7 +884,7 @@ nv67_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -910,7 +910,7 @@ nv68_chipset = {
.fifo = { 0x00000001, nv40_fifo_new },
.gr = { 0x00000001, nv44_gr_new },
.mpeg = { 0x00000001, nv44_mpeg_new },
.pm = nv40_pm_new,
.pm = { 0x00000001, nv40_pm_new },
.sw = nv10_sw_new,
};
@ -941,7 +941,7 @@ nv84_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -973,7 +973,7 @@ nv86_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -1005,7 +1005,7 @@ nv92_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -1037,7 +1037,7 @@ nv94_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -1069,7 +1069,7 @@ nv96_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -1101,7 +1101,7 @@ nv98_chipset = {
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sec = g98_sec_new,
.sw = nv50_sw_new,
};
@ -1133,7 +1133,7 @@ nva0_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt200_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.pm = gt200_pm_new,
.pm = { 0x00000001, gt200_pm_new },
.sw = nv50_sw_new,
.vp = { 0x00000001, g84_vp_new },
};
@ -1168,7 +1168,7 @@ nva3_chipset = {
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.pm = { 0x00000001, gt215_pm_new },
.sw = nv50_sw_new,
};
@ -1201,7 +1201,7 @@ nva5_chipset = {
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.pm = { 0x00000001, gt215_pm_new },
.sw = nv50_sw_new,
};
@ -1234,7 +1234,7 @@ nva8_chipset = {
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.pm = { 0x00000001, gt215_pm_new },
.sw = nv50_sw_new,
};
@ -1265,7 +1265,7 @@ nvaa_chipset = {
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sec = g98_sec_new,
.sw = nv50_sw_new,
};
@ -1297,7 +1297,7 @@ nvac_chipset = {
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.pm = { 0x00000001, g84_pm_new },
.sec = g98_sec_new,
.sw = nv50_sw_new,
};
@ -1331,7 +1331,7 @@ nvaf_chipset = {
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = { 0x00000001, mcp89_msvld_new },
.pm = gt215_pm_new,
.pm = { 0x00000001, gt215_pm_new },
.sw = nv50_sw_new,
};
@ -1367,7 +1367,7 @@ nvc0_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1403,7 +1403,7 @@ nvc1_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf108_pm_new,
.pm = { 0x00000001, gf108_pm_new },
.sw = gf100_sw_new,
};
@ -1439,7 +1439,7 @@ nvc3_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1475,7 +1475,7 @@ nvc4_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1511,7 +1511,7 @@ nvc8_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1547,7 +1547,7 @@ nvce_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1583,7 +1583,7 @@ nvcf_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.pm = { 0x00000001, gf100_pm_new },
.sw = gf100_sw_new,
};
@ -1618,7 +1618,7 @@ nvd7_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf117_pm_new,
.pm = { 0x00000001, gf117_pm_new },
.sw = gf100_sw_new,
};
@ -1654,7 +1654,7 @@ nvd9_chipset = {
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf117_pm_new,
.pm = { 0x00000001, gf117_pm_new },
.sw = gf100_sw_new,
};
@ -1691,7 +1691,7 @@ nve4_chipset = {
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.pm = { 0x00000001, gk104_pm_new },
.sw = gf100_sw_new,
};
@ -1728,7 +1728,7 @@ nve6_chipset = {
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.pm = { 0x00000001, gk104_pm_new },
.sw = gf100_sw_new,
};
@ -1765,7 +1765,7 @@ nve7_chipset = {
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.pm = { 0x00000001, gk104_pm_new },
.sw = gf100_sw_new,
};
@ -1790,7 +1790,7 @@ nvea_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk20a_fifo_new },
.gr = { 0x00000001, gk20a_gr_new },
.pm = gk104_pm_new,
.pm = { 0x00000001, gk104_pm_new },
.sw = gf100_sw_new,
};
@ -3162,7 +3162,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_PM , pm);
_(NVKM_ENGINE_SEC , sec);
_(NVKM_ENGINE_SEC2 , sec2);
_(NVKM_ENGINE_SW , sw);

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
View File

@ -858,11 +858,11 @@ nvkm_pm = {
int
nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device,
int index, struct nvkm_pm *pm)
enum nvkm_subdev_type type, int inst, struct nvkm_pm *pm)
{
pm->func = func;
INIT_LIST_HEAD(&pm->domains);
INIT_LIST_HEAD(&pm->sources);
spin_lock_init(&pm->client.lock);
return nvkm_engine_ctor(&nvkm_pm, device, index, true, &pm->engine);
return nvkm_engine_ctor(&nvkm_pm, device, type, inst, true, &pm->engine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.c
View File

@ -159,7 +159,7 @@ g84_pm[] = {
};
int
g84_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
g84_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return nv40_pm_new_(g84_pm, device, index, ppm);
return nv40_pm_new_(g84_pm, device, type, inst, ppm);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c
View File

@ -187,7 +187,7 @@ gf100_pm_ = {
int
gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device,
int index, struct nvkm_pm **ppm)
enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
struct nvkm_pm *pm;
u32 mask;
@ -196,7 +196,7 @@ gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device,
if (!(pm = *ppm = kzalloc(sizeof(*pm), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_pm_ctor(&gf100_pm_, device, index, pm);
ret = nvkm_pm_ctor(&gf100_pm_, device, type, inst, pm);
if (ret)
return ret;
@ -237,7 +237,7 @@ gf100_pm = {
};
int
gf100_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gf100_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return gf100_pm_new_(&gf100_pm, device, index, ppm);
return gf100_pm_new_(&gf100_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
View File

@ -9,8 +9,8 @@ struct gf100_pm_func {
const struct nvkm_specdom *doms_part;
};
int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *,
int index, struct nvkm_pm **);
int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_pm **);
extern const struct nvkm_funcdom gf100_perfctr_func;
extern const struct nvkm_specdom gf100_pm_gpc[];

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.c
View File

@ -60,7 +60,7 @@ gf108_pm = {
};
int
gf108_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gf108_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return gf100_pm_new_(&gf108_pm, device, index, ppm);
return gf100_pm_new_(&gf108_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.c
View File

@ -74,7 +74,7 @@ gf117_pm = {
};
int
gf117_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gf117_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return gf100_pm_new_(&gf117_pm, device, index, ppm);
return gf100_pm_new_(&gf117_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.c
View File

@ -178,7 +178,7 @@ gk104_pm = {
};
int
gk104_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gk104_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return gf100_pm_new_(&gk104_pm, device, index, ppm);
return gf100_pm_new_(&gk104_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.c
View File

@ -151,7 +151,7 @@ gt200_pm[] = {
};
int
gt200_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gt200_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return nv40_pm_new_(gt200_pm, device, index, ppm);
return nv40_pm_new_(gt200_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.c
View File

@ -132,7 +132,7 @@ gt215_pm[] = {
};
int
gt215_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
gt215_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return nv40_pm_new_(gt215_pm, device, index, ppm);
return nv40_pm_new_(gt215_pm, device, type, inst, ppm);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c
View File

@ -80,7 +80,7 @@ nv40_pm_ = {
int
nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device,
int index, struct nvkm_pm **ppm)
enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
struct nv40_pm *pm;
int ret;
@ -89,7 +89,7 @@ nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device,
return -ENOMEM;
*ppm = &pm->base;
ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base);
ret = nvkm_pm_ctor(&nv40_pm_, device, type, inst, &pm->base);
if (ret)
return ret;
@ -117,7 +117,7 @@ nv40_pm[] = {
};
int
nv40_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
nv40_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return nv40_pm_new_(nv40_pm, device, index, ppm);
return nv40_pm_new_(nv40_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
View File

@ -9,7 +9,7 @@ struct nv40_pm {
u32 sequence;
};
int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *,
int index, struct nvkm_pm **);
int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_pm **);
extern const struct nvkm_funcdom nv40_perfctr_func;
#endif

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.c
View File

@ -169,7 +169,7 @@ nv50_pm[] = {
};
int
nv50_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
nv50_pm_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_pm **ppm)
{
return nv40_pm_new_(nv50_pm, device, index, ppm);
return nv40_pm_new_(nv50_pm, device, type, inst, ppm);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
View File

@ -4,8 +4,8 @@
#define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
#include <engine/pm.h>
int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *,
int index, struct nvkm_pm *);
int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_pm *);
struct nvkm_pm_func {
void (*fini)(struct nvkm_pm *);