drm/exynos: dsi: add support for Exynos5433
This patch adds support for Exynos5433 mipi dsi. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Hyungwon Hwang
Inki Dae
parent
0ff03fd164
commit
e6f988a458
@ -6,6 +6,7 @@ Required properties:
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"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
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"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
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"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
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"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
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- reg: physical base address and length of the registers set for the device
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- interrupts: should contain DSI interrupt
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- clocks: list of clock specifiers, must contain an entry for each required
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@ -47,7 +47,7 @@ config DRM_EXYNOS_DPI
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config DRM_EXYNOS_DSI
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bool "EXYNOS DRM MIPI-DSI driver support"
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depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
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depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS5433_DECON || DRM_EXYNOS7_DECON)
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select DRM_MIPI_DSI
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select DRM_PANEL
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default n
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@ -132,6 +132,7 @@
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#define DSIM_INT_PLL_STABLE (1 << 31)
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#define DSIM_INT_SW_RST_RELEASE (1 << 30)
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#define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
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#define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28)
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#define DSIM_INT_BTA (1 << 25)
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#define DSIM_INT_FRAME_DONE (1 << 24)
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#define DSIM_INT_RX_TIMEOUT (1 << 21)
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@ -180,6 +181,8 @@
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/* DSIM_PHYCTRL */
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#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
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#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30)
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#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14)
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/* DSIM_PHYTIMING */
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#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
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@ -211,7 +214,9 @@
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REG_ADDR((dsi), (reg_idx)))
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#define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
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static char *clk_names[2] = { "bus_clk", "sclk_mipi" };
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static char *clk_names[5] = { "bus_clk", "sclk_mipi",
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"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
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"sclk_rgb_vclk_to_dsim0" };
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enum exynos_dsi_transfer_type {
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EXYNOS_DSI_TX,
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@ -341,6 +346,30 @@ static unsigned int exynos_reg_ofs[] = {
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[DSIM_PHYTIMING2_REG] = 0x6c,
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};
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static unsigned int exynos5433_reg_ofs[] = {
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[DSIM_STATUS_REG] = 0x04,
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[DSIM_SWRST_REG] = 0x0C,
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[DSIM_CLKCTRL_REG] = 0x10,
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[DSIM_TIMEOUT_REG] = 0x14,
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[DSIM_CONFIG_REG] = 0x18,
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[DSIM_ESCMODE_REG] = 0x1C,
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[DSIM_MDRESOL_REG] = 0x20,
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[DSIM_MVPORCH_REG] = 0x24,
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[DSIM_MHPORCH_REG] = 0x28,
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[DSIM_MSYNC_REG] = 0x2C,
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[DSIM_INTSRC_REG] = 0x34,
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[DSIM_INTMSK_REG] = 0x38,
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[DSIM_PKTHDR_REG] = 0x3C,
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[DSIM_PAYLOAD_REG] = 0x40,
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[DSIM_RXFIFO_REG] = 0x44,
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[DSIM_FIFOCTRL_REG] = 0x4C,
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[DSIM_PLLCTRL_REG] = 0x94,
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[DSIM_PHYCTRL_REG] = 0xA4,
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[DSIM_PHYTIMING_REG] = 0xB4,
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[DSIM_PHYTIMING1_REG] = 0xB8,
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[DSIM_PHYTIMING2_REG] = 0xBC,
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};
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enum reg_value_idx {
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RESET_TYPE,
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PLL_TIMER,
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@ -377,6 +406,24 @@ static unsigned int reg_values[] = {
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[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
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};
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static unsigned int exynos5433_reg_values[] = {
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[RESET_TYPE] = DSIM_FUNCRST,
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[PLL_TIMER] = 22200,
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[STOP_STATE_CNT] = 0xa,
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[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
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[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
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[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
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[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
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[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
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[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
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[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
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[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
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[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
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[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
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[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
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[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
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};
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static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
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.reg_ofs = exynos_reg_ofs,
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.plltmr_reg = 0x50,
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@ -422,6 +469,17 @@ static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
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.reg_values = reg_values,
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};
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static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
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.reg_ofs = exynos5433_reg_ofs,
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.plltmr_reg = 0xa0,
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.has_clklane_stop = 1,
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.num_clks = 5,
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.max_freq = 1500,
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.wait_for_reset = 0,
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.num_bits_resol = 12,
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.reg_values = exynos5433_reg_values,
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};
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static struct of_device_id exynos_dsi_of_match[] = {
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{ .compatible = "samsung,exynos3250-mipi-dsi",
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.data = &exynos3_dsi_driver_data },
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@ -431,6 +489,8 @@ static struct of_device_id exynos_dsi_of_match[] = {
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.data = &exynos4415_dsi_driver_data },
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{ .compatible = "samsung,exynos5410-mipi-dsi",
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.data = &exynos5_dsi_driver_data },
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{ .compatible = "samsung,exynos5433-mipi-dsi",
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.data = &exynos5433_dsi_driver_data },
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{ }
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};
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@ -682,6 +742,14 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
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DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
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}
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static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
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{
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u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG);
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reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
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DSIM_LANE_EN(lane));
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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}
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static int exynos_dsi_init_link(struct exynos_dsi *dsi)
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{
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struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
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@ -754,17 +822,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
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return -EINVAL;
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}
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reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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reg |= DSIM_LANE_EN_CLK;
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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lanes_mask = BIT(dsi->lanes) - 1;
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reg |= DSIM_LANE_EN(lanes_mask);
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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/*
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* Use non-continuous clock mode if the periparal wants and
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* host controller supports
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@ -776,8 +833,11 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
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if (driver_data->has_clklane_stop &&
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dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
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reg |= DSIM_CLKLANE_STOP;
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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}
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DSI_WRITE(dsi, DSIM_CONFIG_REG, reg);
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lanes_mask = BIT(dsi->lanes) - 1;
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exynos_dsi_enable_lane(dsi, lanes_mask);
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/* Check clock and data lane state are stop state */
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timeout = 100;
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@ -1189,13 +1249,16 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
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DSI_WRITE(dsi, DSIM_INTSRC_REG, status);
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if (status & DSIM_INT_SW_RST_RELEASE) {
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u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
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u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
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DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE |
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DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE);
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DSI_WRITE(dsi, DSIM_INTMSK_REG, mask);
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complete(&dsi->completed);
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return IRQ_HANDLED;
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}
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if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
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if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
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DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE)))
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return IRQ_HANDLED;
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if (exynos_dsi_transfer_finish(dsi))
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@ -1237,6 +1300,10 @@ static int exynos_dsi_init(struct exynos_dsi *dsi)
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exynos_dsi_reset(dsi);
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exynos_dsi_enable_irq(dsi);
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if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
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exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
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exynos_dsi_enable_clock(dsi);
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if (driver_data->wait_for_reset)
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exynos_dsi_wait_for_reset(dsi);
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@ -1811,6 +1878,9 @@ static int exynos_dsi_probe(struct platform_device *pdev)
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dsi->clks = devm_kzalloc(dev,
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sizeof(*dsi->clks) * dsi->driver_data->num_clks,
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GFP_KERNEL);
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if (!dsi->clks)
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return -ENOMEM;
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for (i = 0; i < dsi->driver_data->num_clks; i++) {
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dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
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if (IS_ERR(dsi->clks[i])) {
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