Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for 3.17. It contains: - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates - MIPS ptrace updates and cleanups - various fixes that will also go to -stable - a number of cleanups and small non-critical fixes. - NUMA support for the Loongson 3. - more support for MSA - support for MAAR - various FP enhancements and fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) MIPS: jz4740: remove unnecessary null test before debugfs_remove MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive MIPS: ZBOOT: implement stack protector in compressed boot phase MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT MIPS: Bonito64: remove a duplicate define MIPS: Malta: initialise MAARs MIPS: Initialise MAARs MIPS: detect presence of MAARs MIPS: define MAAR register accessors & bits MIPS: mark MSA experimental MIPS: Don't build MSA support unless it can be used MIPS: consistently clear MSA flags when starting & copying threads MIPS: 16 byte align MSA vector context MIPS: disable preemption whilst initialising MSA MIPS: ensure MSA gets disabled during boot MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains MIPS: fix MSA context for tasks which don't use FP first MIPS: init upper 64b of vector registers when MSA is first used MIPS: save/disable MSA in lose_fpu MIPS: preserve scalar FP CSR when switching vector context ...
This commit is contained in:
Linus Torvalds
@@ -22,24 +22,27 @@
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#define DSP_CONTROL 77
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#define ACX 78
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#ifndef __KERNEL__
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/*
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* This struct defines the way the registers are stored on the stack during a
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* system call/exception. As usual the registers k0/k1 aren't being saved.
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* This struct defines the registers as used by PTRACE_{GET,SET}REGS. The
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* format is the same for both 32- and 64-bit processes. Registers for 32-bit
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* processes are sign extended.
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*/
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#ifdef __KERNEL__
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struct user_pt_regs {
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#else
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struct pt_regs {
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#endif
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/* Saved main processor registers. */
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unsigned long regs[32];
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__u64 regs[32];
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/* Saved special registers. */
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unsigned long cp0_status;
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unsigned long hi;
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unsigned long lo;
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unsigned long cp0_badvaddr;
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unsigned long cp0_cause;
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unsigned long cp0_epc;
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__u64 lo;
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__u64 hi;
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__u64 cp0_epc;
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__u64 cp0_badvaddr;
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__u64 cp0_status;
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__u64 cp0_cause;
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} __attribute__ ((aligned (8)));
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#endif /* __KERNEL__ */
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/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
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#define PTRACE_GETREGS 12
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206
arch/mips/include/uapi/asm/reg.h
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206
arch/mips/include/uapi/asm/reg.h
Normal file
@@ -0,0 +1,206 @@
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/*
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* Various register offset definitions for debuggers, core file
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* examiners and whatnot.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1999 Ralf Baechle
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* Copyright (C) 1995, 1999 Silicon Graphics
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*/
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#ifndef __UAPI_ASM_MIPS_REG_H
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#define __UAPI_ASM_MIPS_REG_H
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#define MIPS32_EF_R0 6
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#define MIPS32_EF_R1 7
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#define MIPS32_EF_R2 8
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#define MIPS32_EF_R3 9
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#define MIPS32_EF_R4 10
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#define MIPS32_EF_R5 11
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#define MIPS32_EF_R6 12
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#define MIPS32_EF_R7 13
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#define MIPS32_EF_R8 14
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#define MIPS32_EF_R9 15
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#define MIPS32_EF_R10 16
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#define MIPS32_EF_R11 17
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#define MIPS32_EF_R12 18
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#define MIPS32_EF_R13 19
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#define MIPS32_EF_R14 20
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#define MIPS32_EF_R15 21
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#define MIPS32_EF_R16 22
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#define MIPS32_EF_R17 23
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#define MIPS32_EF_R18 24
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#define MIPS32_EF_R19 25
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#define MIPS32_EF_R20 26
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#define MIPS32_EF_R21 27
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#define MIPS32_EF_R22 28
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#define MIPS32_EF_R23 29
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#define MIPS32_EF_R24 30
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#define MIPS32_EF_R25 31
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/*
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* k0/k1 unsaved
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*/
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#define MIPS32_EF_R26 32
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#define MIPS32_EF_R27 33
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#define MIPS32_EF_R28 34
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#define MIPS32_EF_R29 35
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#define MIPS32_EF_R30 36
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#define MIPS32_EF_R31 37
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/*
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* Saved special registers
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*/
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#define MIPS32_EF_LO 38
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#define MIPS32_EF_HI 39
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#define MIPS32_EF_CP0_EPC 40
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#define MIPS32_EF_CP0_BADVADDR 41
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#define MIPS32_EF_CP0_STATUS 42
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#define MIPS32_EF_CP0_CAUSE 43
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#define MIPS32_EF_UNUSED0 44
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#define MIPS32_EF_SIZE 180
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#define MIPS64_EF_R0 0
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#define MIPS64_EF_R1 1
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#define MIPS64_EF_R2 2
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#define MIPS64_EF_R3 3
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#define MIPS64_EF_R4 4
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#define MIPS64_EF_R5 5
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#define MIPS64_EF_R6 6
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#define MIPS64_EF_R7 7
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#define MIPS64_EF_R8 8
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#define MIPS64_EF_R9 9
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#define MIPS64_EF_R10 10
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#define MIPS64_EF_R11 11
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#define MIPS64_EF_R12 12
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#define MIPS64_EF_R13 13
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#define MIPS64_EF_R14 14
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#define MIPS64_EF_R15 15
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#define MIPS64_EF_R16 16
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#define MIPS64_EF_R17 17
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#define MIPS64_EF_R18 18
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#define MIPS64_EF_R19 19
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#define MIPS64_EF_R20 20
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#define MIPS64_EF_R21 21
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#define MIPS64_EF_R22 22
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#define MIPS64_EF_R23 23
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#define MIPS64_EF_R24 24
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#define MIPS64_EF_R25 25
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/*
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* k0/k1 unsaved
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*/
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#define MIPS64_EF_R26 26
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#define MIPS64_EF_R27 27
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#define MIPS64_EF_R28 28
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#define MIPS64_EF_R29 29
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#define MIPS64_EF_R30 30
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#define MIPS64_EF_R31 31
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/*
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* Saved special registers
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*/
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#define MIPS64_EF_LO 32
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#define MIPS64_EF_HI 33
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#define MIPS64_EF_CP0_EPC 34
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#define MIPS64_EF_CP0_BADVADDR 35
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#define MIPS64_EF_CP0_STATUS 36
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#define MIPS64_EF_CP0_CAUSE 37
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#define MIPS64_EF_SIZE 304 /* size in bytes */
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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#define EF_R0 MIPS32_EF_R0
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#define EF_R1 MIPS32_EF_R1
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#define EF_R2 MIPS32_EF_R2
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#define EF_R3 MIPS32_EF_R3
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#define EF_R4 MIPS32_EF_R4
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#define EF_R5 MIPS32_EF_R5
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#define EF_R6 MIPS32_EF_R6
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#define EF_R7 MIPS32_EF_R7
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#define EF_R8 MIPS32_EF_R8
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#define EF_R9 MIPS32_EF_R9
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#define EF_R10 MIPS32_EF_R10
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#define EF_R11 MIPS32_EF_R11
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#define EF_R12 MIPS32_EF_R12
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#define EF_R13 MIPS32_EF_R13
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#define EF_R14 MIPS32_EF_R14
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#define EF_R15 MIPS32_EF_R15
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#define EF_R16 MIPS32_EF_R16
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#define EF_R17 MIPS32_EF_R17
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#define EF_R18 MIPS32_EF_R18
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#define EF_R19 MIPS32_EF_R19
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#define EF_R20 MIPS32_EF_R20
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#define EF_R21 MIPS32_EF_R21
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#define EF_R22 MIPS32_EF_R22
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#define EF_R23 MIPS32_EF_R23
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#define EF_R24 MIPS32_EF_R24
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#define EF_R25 MIPS32_EF_R25
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#define EF_R26 MIPS32_EF_R26
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#define EF_R27 MIPS32_EF_R27
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#define EF_R28 MIPS32_EF_R28
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#define EF_R29 MIPS32_EF_R29
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#define EF_R30 MIPS32_EF_R30
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#define EF_R31 MIPS32_EF_R31
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#define EF_LO MIPS32_EF_LO
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#define EF_HI MIPS32_EF_HI
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#define EF_CP0_EPC MIPS32_EF_CP0_EPC
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#define EF_CP0_BADVADDR MIPS32_EF_CP0_BADVADDR
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#define EF_CP0_STATUS MIPS32_EF_CP0_STATUS
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#define EF_CP0_CAUSE MIPS32_EF_CP0_CAUSE
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#define EF_UNUSED0 MIPS32_EF_UNUSED0
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#define EF_SIZE MIPS32_EF_SIZE
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#elif _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
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#define EF_R0 MIPS64_EF_R0
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#define EF_R1 MIPS64_EF_R1
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#define EF_R2 MIPS64_EF_R2
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#define EF_R3 MIPS64_EF_R3
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#define EF_R4 MIPS64_EF_R4
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#define EF_R5 MIPS64_EF_R5
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#define EF_R6 MIPS64_EF_R6
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#define EF_R7 MIPS64_EF_R7
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#define EF_R8 MIPS64_EF_R8
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#define EF_R9 MIPS64_EF_R9
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#define EF_R10 MIPS64_EF_R10
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#define EF_R11 MIPS64_EF_R11
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#define EF_R12 MIPS64_EF_R12
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#define EF_R13 MIPS64_EF_R13
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#define EF_R14 MIPS64_EF_R14
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#define EF_R15 MIPS64_EF_R15
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#define EF_R16 MIPS64_EF_R16
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#define EF_R17 MIPS64_EF_R17
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#define EF_R18 MIPS64_EF_R18
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#define EF_R19 MIPS64_EF_R19
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#define EF_R20 MIPS64_EF_R20
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#define EF_R21 MIPS64_EF_R21
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#define EF_R22 MIPS64_EF_R22
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#define EF_R23 MIPS64_EF_R23
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#define EF_R24 MIPS64_EF_R24
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#define EF_R25 MIPS64_EF_R25
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#define EF_R26 MIPS64_EF_R26
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#define EF_R27 MIPS64_EF_R27
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#define EF_R28 MIPS64_EF_R28
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#define EF_R29 MIPS64_EF_R29
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#define EF_R30 MIPS64_EF_R30
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#define EF_R31 MIPS64_EF_R31
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#define EF_LO MIPS64_EF_LO
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#define EF_HI MIPS64_EF_HI
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#define EF_CP0_EPC MIPS64_EF_CP0_EPC
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#define EF_CP0_BADVADDR MIPS64_EF_CP0_BADVADDR
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#define EF_CP0_STATUS MIPS64_EF_CP0_STATUS
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#define EF_CP0_CAUSE MIPS64_EF_CP0_CAUSE
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#define EF_SIZE MIPS64_EF_SIZE
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
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#endif /* __UAPI_ASM_MIPS_REG_H */
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