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memory: tegra: Add SWGROUP names

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Subsequent patches will add debugfs files that print the status of the
SWGROUPs. Add a new names field and complement the SoC tables with the
names of the individual SWGROUPs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2015-01-23 09:45:35 +01:00
parent b787f68c36
commit e660df07ab
4 changed files with 56 additions and 55 deletions
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32
drivers/memory/tegra/tegra114.c
View File

@ -896,22 +896,22 @@ static const struct tegra_mc_client tegra114_mc_clients[] = {
};
static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
};
static void tegra114_flush_dcache(struct page *page, unsigned long offset,

46
drivers/memory/tegra/tegra124.c
View File

@ -934,29 +934,29 @@ static const struct tegra_mc_client tegra124_mc_clients[] = {
};
static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
{ .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
};
#ifdef CONFIG_ARCH_TEGRA_124_SOC

32
drivers/memory/tegra/tegra30.c
View File

@ -918,22 +918,22 @@ static const struct tegra_mc_client tegra30_mc_clients[] = {
};
static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
{ .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
{ .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
};
static void tegra30_flush_dcache(struct page *page, unsigned long offset,

1
include/soc/tegra/mc.h
View File

@ -40,6 +40,7 @@ struct tegra_mc_client {
};
struct tegra_smmu_swgroup {
const char *name;
unsigned int swgroup;
unsigned int reg;
};