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tty: serial: meson: Make some bit of the REG5 register writable

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Make the internal clock source mux and divider writeable, allowing the
uart to deviate from the settings intially applied by the ROMCode and
using the most appropriate clocks.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Link: https://lore.kernel.org/r/20220225073922.3947-5-yu.tu@amlogic.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Yu Tu 2022-02-25 15:39:20 +08:00 committed by Greg Kroah-Hartman
parent 44023b8e1f
commit e5fc2b9984
1 changed files with 2 additions and 2 deletions
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4
drivers/tty/serial/meson_uart.c
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@ -686,7 +686,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
CLK_SET_RATE_NO_REPARENT,
port->membase + AML_UART_REG5,
26, 2,
CLK_DIVIDER_READ_ONLY,
CLK_DIVIDER_ROUND_CLOSEST,
xtal_div_table, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
CLK_SET_RATE_PARENT,
port->membase + AML_UART_REG5,
24, 0x1,
CLK_MUX_READ_ONLY,
CLK_MUX_ROUND_CLOSEST,
&use_xtal_mux_table, NULL);
if (IS_ERR(hw))