forked from Minki/linux
fpga: altera-cvp: Add Stratix10 (V2) Support
Add Stratix10 specific functions that use a credit mechanism to throttle data to the CvP FIFOs. Add a private structure with function pointers for V1 vs V2 functions. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
This commit is contained in:
Thor Thayer
Moritz Fischer
parent
d2083d040a
commit
e58915179f
@ -45,11 +45,11 @@ config FPGA_MGR_ALTERA_PS_SPI
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using the passive serial interface over SPI.
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config FPGA_MGR_ALTERA_CVP
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tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
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tristate "Altera CvP FPGA Manager"
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depends on PCI
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help
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FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
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and Arria 10 Altera FPGAs using the CvP interface over PCIe.
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FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
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Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
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config FPGA_MGR_ZYNQ_FPGA
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tristate "Xilinx Zynq FPGA"
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@ -43,16 +43,34 @@
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#define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
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#define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
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#define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
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#define VSE_CVP_PROG_CTRL_MASK GENMASK(1, 0)
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#define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
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#define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
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#define V1_VSEC_OFFSET 0x200 /* Vendor Specific Offset V1 */
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/* V2 Defines */
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#define VSE_CVP_TX_CREDITS 0x49 /* 8bit */
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#define V2_CREDIT_TIMEOUT_US 20000
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#define V2_CHECK_CREDIT_US 10
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#define V2_POLL_TIMEOUT_US 1000000
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#define V2_USER_TIMEOUT_US 500000
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#define V1_POLL_TIMEOUT_US 10
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#define DRV_NAME "altera-cvp"
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#define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
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/* Write block sizes */
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#define ALTERA_CVP_V1_SIZE 4
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#define ALTERA_CVP_V2_SIZE 4096
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/* Optional CvP config error status check for debugging */
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static bool altera_cvp_chkcfg;
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struct cvp_priv;
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struct altera_cvp_conf {
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struct fpga_manager *mgr;
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struct pci_dev *pci_dev;
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@ -61,9 +79,27 @@ struct altera_cvp_conf {
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u32 data);
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char mgr_name[64];
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u8 numclks;
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u32 sent_packets;
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u32 vsec_offset;
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const struct cvp_priv *priv;
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};
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struct cvp_priv {
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void (*switch_clk)(struct altera_cvp_conf *conf);
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int (*clear_state)(struct altera_cvp_conf *conf);
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int (*wait_credit)(struct fpga_manager *mgr, u32 blocks);
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size_t block_size;
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int poll_time_us;
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int user_time_us;
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};
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static int altera_read_config_byte(struct altera_cvp_conf *conf,
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int where, u8 *val)
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{
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return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where,
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val);
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}
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static int altera_read_config_dword(struct altera_cvp_conf *conf,
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int where, u32 *val)
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{
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@ -159,6 +195,73 @@ static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
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return 0;
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}
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/*
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* CvP Version2 Functions
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* Recent Intel FPGAs use a credit mechanism to throttle incoming
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* bitstreams and a different method of clearing the state.
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*/
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static int altera_cvp_v2_clear_state(struct altera_cvp_conf *conf)
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{
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u32 val;
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int ret;
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/* Clear the START_XFER and CVP_CONFIG bits */
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ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error reading CVP Program Control Register\n");
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return ret;
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}
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val &= ~VSE_CVP_PROG_CTRL_MASK;
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ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error writing CVP Program Control Register\n");
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return ret;
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}
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return altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
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conf->priv->poll_time_us);
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}
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static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr,
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u32 blocks)
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{
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u32 timeout = V2_CREDIT_TIMEOUT_US / V2_CHECK_CREDIT_US;
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struct altera_cvp_conf *conf = mgr->priv;
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int ret;
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u8 val;
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do {
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ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"Error reading CVP Credit Register\n");
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return ret;
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}
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/* Return if there is space in FIFO */
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if (val - (u8)conf->sent_packets)
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return 0;
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ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE);
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if (ret) {
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dev_err(&conf->pci_dev->dev,
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"CE Bit error credit reg[0x%x]:sent[0x%x]\n",
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val, conf->sent_packets);
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return -EAGAIN;
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}
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/* Limit the check credit byte traffic */
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usleep_range(V2_CHECK_CREDIT_US, V2_CHECK_CREDIT_US + 1);
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} while (timeout--);
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dev_err(&conf->pci_dev->dev, "Timeout waiting for credit\n");
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return -ETIMEDOUT;
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}
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static int altera_cvp_send_block(struct altera_cvp_conf *conf,
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const u32 *data, size_t len)
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{
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@ -200,10 +303,12 @@ static int altera_cvp_teardown(struct fpga_manager *mgr,
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* - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
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* writes to the HIP
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*/
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altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
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conf->priv->poll_time_us);
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if (ret)
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dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
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@ -265,7 +370,18 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
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* STEP 3
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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altera_cvp_dummy_write(conf);
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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if (conf->priv->clear_state) {
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ret = conf->priv->clear_state(conf);
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if (ret) {
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dev_err(&mgr->dev, "Problem clearing out state\n");
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return ret;
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}
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}
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conf->sent_packets = 0;
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/* STEP 4 - set CVP_CONFIG bit */
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altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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@ -273,9 +389,10 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
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val |= VSE_CVP_PROG_CTRL_CONFIG;
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
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/* STEP 5 - poll CVP_CONFIG READY for 1 with timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
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VSE_CVP_STATUS_CFG_RDY, 10);
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VSE_CVP_STATUS_CFG_RDY,
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conf->priv->poll_time_us);
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if (ret) {
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dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
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return ret;
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@ -285,7 +402,16 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
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* STEP 6
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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altera_cvp_dummy_write(conf);
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if (conf->priv->switch_clk)
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conf->priv->switch_clk(conf);
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if (altera_cvp_chkcfg) {
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ret = altera_cvp_chk_error(mgr, 0);
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if (ret) {
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dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
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return ret;
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}
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}
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/* STEP 7 - set START_XFER */
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altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
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@ -293,11 +419,12 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
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altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
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/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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if (conf->priv->switch_clk) {
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altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
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}
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return 0;
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}
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@ -315,11 +442,22 @@ static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
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done = 0;
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while (remaining) {
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len = min(sizeof(u32), remaining);
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/* Use credit throttling if available */
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if (conf->priv->wait_credit) {
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status = conf->priv->wait_credit(mgr, done);
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if (status) {
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dev_err(&conf->pci_dev->dev,
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"Wait Credit ERR: 0x%x\n", status);
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return status;
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}
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}
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len = min(conf->priv->block_size, remaining);
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altera_cvp_send_block(conf, data, len);
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data++;
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data += len / sizeof(u32);
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done += len;
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remaining -= len;
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conf->sent_packets++;
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/*
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* STEP 10 (optional) and STEP 11
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@ -369,7 +507,8 @@ static int altera_cvp_write_complete(struct fpga_manager *mgr,
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/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
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mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
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ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
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ret = altera_cvp_wait_status(conf, mask, mask,
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conf->priv->user_time_us);
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if (ret)
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dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
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@ -383,6 +522,21 @@ static const struct fpga_manager_ops altera_cvp_ops = {
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.write_complete = altera_cvp_write_complete,
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};
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static const struct cvp_priv cvp_priv_v1 = {
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.switch_clk = altera_cvp_dummy_write,
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.block_size = ALTERA_CVP_V1_SIZE,
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.poll_time_us = V1_POLL_TIMEOUT_US,
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.user_time_us = TIMEOUT_US,
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};
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static const struct cvp_priv cvp_priv_v2 = {
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.clear_state = altera_cvp_v2_clear_state,
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.wait_credit = altera_cvp_v2_wait_for_credit,
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.block_size = ALTERA_CVP_V2_SIZE,
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.poll_time_us = V2_POLL_TIMEOUT_US,
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.user_time_us = V2_USER_TIMEOUT_US,
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};
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static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
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{
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return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
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@ -484,6 +638,11 @@ static int altera_cvp_probe(struct pci_dev *pdev,
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conf->pci_dev = pdev;
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conf->write_data = altera_cvp_write_data_iomem;
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if (conf->vsec_offset == V1_VSEC_OFFSET)
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conf->priv = &cvp_priv_v1;
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else
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conf->priv = &cvp_priv_v2;
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conf->map = pci_iomap(pdev, CVP_BAR, 0);
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if (!conf->map) {
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dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
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