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arm64: dts: sparx5: Add Sparx5 SoC DPLL clock

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This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.

Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Lars Povlsen 2020-06-15 15:32:41 +02:00 committed by Arnd Bergmann
parent 39c8378a1c
commit e4e06a50b0
1 changed files with 23 additions and 16 deletions
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39
arch/arm64/boot/dts/microchip/sparx5.dtsi
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@ -72,20 +72,29 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
clocks: clocks {
#address-cells = <2>;
#size-cells = <1>;
ranges;
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <625000000>;
};
lcpll_clk: lcpll-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2500000000>;
};
clks: clock-controller@61110000c {
compatible = "microchip,sparx5-dpll";
#clock-cells = <1>;
clocks = <&lcpll_clk>;
reg = <0x6 0x1110000c 0x24>;
};
ahb_clk: ahb-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
sys_clk: sys-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <625000000>;
};
axi: axi@600000000 {
@ -161,8 +170,6 @@
pins = "GPIO_26", "GPIO_27";
function = "uart2";
};
};
};
};