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PCI: tegra: Overhaul regulator usage

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The current usage of regulators for the Tegra PCIe block is wrong. It
doesn't accurately reflect the actual supply inputs of the IP block and
therefore isn't as flexible as it should be. Rectify this by describing
all possible supply inputs in the device tree binding documentation and
deprecate the old supply properties.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Thierry Reding 2014-05-28 16:49:11 +02:00 committed by Stephen Warren
parent 7171511eae
commit e4958675b6
1 changed files with 32 additions and 3 deletions
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35
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
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@ -14,9 +14,6 @@ Required properties:
- interrupt-names: Must include the following entries: - interrupt-names: Must include the following entries:
"intr": The Tegra interrupt that is asserted for controller interrupts "intr": The Tegra interrupt that is asserted for controller interrupts
"msi": The Tegra interrupt that is asserted when an MSI is received "msi": The Tegra interrupt that is asserted when an MSI is received
- pex-clk-supply: Supply voltage for internal reference clock
- vdd-supply: Power supply for controller (1.05V)
- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
- bus-range: Range of bus numbers associated with this controller - bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3) - #address-cells: Address representation for root ports (must be 3)
- cell 0 specifies the bus and device numbers of the root port: - cell 0 specifies the bus and device numbers of the root port:
@ -60,6 +57,38 @@ Required properties:
- afi - afi
- pcie_x - pcie_x
Power supplies for Tegra20:
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
supply 1.05 V.
- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
supply 1.05 V.
- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
Power supplies for Tegra30:
- Required:
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
supply 1.05 V.
- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
supply 1.05 V.
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
supply 1.8 V.
- hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
Must supply 3.3 V.
- Optional:
- If lanes 0 to 3 are used:
- avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- If lanes 4 or 5 are used:
- avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
Deprecated supplies:
- pex-clk-supply: Supply voltage for internal reference clock
- vdd-supply: Power supply for controller (1.05V)
- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
Root ports are defined as subnodes of the PCIe controller node. Root ports are defined as subnodes of the PCIe controller node.
Required properties: Required properties: