bpf/tests: Minor restructuring of ALU tests
This patch moves the ALU LSH/RSH/ARSH reference computations into the common reference value function. Also fix typo in constants so they now have the intended values. Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20211001130348.3670534-7-johan.almbladh@anyfinetworks.com
This commit is contained in:
Johan Almbladh
Daniel Borkmann
parent
e2f9797b3c
commit
e42fc3c2c4
137
lib/test_bpf.c
137
lib/test_bpf.c
@ -538,6 +538,57 @@ static int bpf_fill_max_jmp_never_taken(struct bpf_test *self)
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return __bpf_fill_max_jmp(self, BPF_JLT, 0);
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}
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/* ALU result computation used in tests */
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static bool __bpf_alu_result(u64 *res, u64 v1, u64 v2, u8 op)
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{
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*res = 0;
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switch (op) {
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case BPF_MOV:
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*res = v2;
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break;
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case BPF_AND:
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*res = v1 & v2;
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break;
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case BPF_OR:
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*res = v1 | v2;
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break;
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case BPF_XOR:
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*res = v1 ^ v2;
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break;
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case BPF_LSH:
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*res = v1 << v2;
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break;
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case BPF_RSH:
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*res = v1 >> v2;
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break;
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case BPF_ARSH:
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*res = v1 >> v2;
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if (v2 > 0 && v1 > S64_MAX)
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*res |= ~0ULL << (64 - v2);
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break;
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case BPF_ADD:
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*res = v1 + v2;
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break;
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case BPF_SUB:
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*res = v1 - v2;
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break;
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case BPF_MUL:
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*res = v1 * v2;
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break;
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case BPF_DIV:
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if (v2 == 0)
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return false;
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*res = div64_u64(v1, v2);
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break;
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case BPF_MOD:
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if (v2 == 0)
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return false;
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div64_u64_rem(v1, v2, res);
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break;
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}
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return true;
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}
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/* Test an ALU shift operation for all valid shift values */
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static int __bpf_fill_alu_shift(struct bpf_test *self, u8 op,
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u8 mode, bool alu32)
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@ -576,37 +627,19 @@ static int __bpf_fill_alu_shift(struct bpf_test *self, u8 op,
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insn[i++] = BPF_ALU32_IMM(op, R1, imm);
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else
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insn[i++] = BPF_ALU32_REG(op, R1, R2);
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switch (op) {
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case BPF_LSH:
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val = (u32)reg << imm;
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break;
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case BPF_RSH:
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val = (u32)reg >> imm;
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break;
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case BPF_ARSH:
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val = (u32)reg >> imm;
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if (imm > 0 && (reg & 0x80000000))
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val |= ~(u32)0 << (32 - imm);
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break;
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}
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if (op == BPF_ARSH)
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reg = (s32)reg;
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else
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reg = (u32)reg;
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__bpf_alu_result(&val, reg, imm, op);
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val = (u32)val;
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} else {
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if (mode == BPF_K)
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insn[i++] = BPF_ALU64_IMM(op, R1, imm);
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else
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insn[i++] = BPF_ALU64_REG(op, R1, R2);
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switch (op) {
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case BPF_LSH:
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val = (u64)reg << imm;
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break;
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case BPF_RSH:
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val = (u64)reg >> imm;
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break;
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case BPF_ARSH:
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val = (u64)reg >> imm;
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if (imm > 0 && reg < 0)
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val |= ~(u64)0 << (64 - imm);
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break;
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}
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__bpf_alu_result(&val, reg, imm, op);
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}
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/*
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@ -799,46 +832,6 @@ static int __bpf_fill_pattern(struct bpf_test *self, void *arg,
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* test is designed to verify e.g. the ALU and ALU64 operations for JITs that
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* emit different code depending on the magnitude of the immediate value.
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*/
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static bool __bpf_alu_result(u64 *res, u64 v1, u64 v2, u8 op)
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{
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*res = 0;
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switch (op) {
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case BPF_MOV:
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*res = v2;
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break;
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case BPF_AND:
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*res = v1 & v2;
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break;
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case BPF_OR:
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*res = v1 | v2;
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break;
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case BPF_XOR:
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*res = v1 ^ v2;
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break;
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case BPF_ADD:
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*res = v1 + v2;
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break;
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case BPF_SUB:
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*res = v1 - v2;
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break;
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case BPF_MUL:
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*res = v1 * v2;
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break;
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case BPF_DIV:
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if (v2 == 0)
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return false;
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*res = div64_u64(v1, v2);
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break;
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case BPF_MOD:
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if (v2 == 0)
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return false;
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div64_u64_rem(v1, v2, res);
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break;
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}
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return true;
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}
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static int __bpf_emit_alu64_imm(struct bpf_test *self, void *arg,
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struct bpf_insn *insns, s64 dst, s64 imm)
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{
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@ -7881,7 +7874,7 @@ static struct bpf_test tests[] = {
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"BPF_ATOMIC | BPF_DW, BPF_CMPXCHG: Test successful return",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789abcdefULL),
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BPF_LD_IMM64(R2, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_STX_MEM(BPF_DW, R10, R1, -40),
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BPF_ATOMIC_OP(BPF_DW, BPF_CMPXCHG, R10, R2, -40),
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@ -7898,7 +7891,7 @@ static struct bpf_test tests[] = {
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"BPF_ATOMIC | BPF_DW, BPF_CMPXCHG: Test successful store",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789abcdefULL),
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BPF_LD_IMM64(R2, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_STX_MEM(BPF_DW, R10, R0, -40),
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BPF_ATOMIC_OP(BPF_DW, BPF_CMPXCHG, R10, R2, -40),
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@ -7916,7 +7909,7 @@ static struct bpf_test tests[] = {
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"BPF_ATOMIC | BPF_DW, BPF_CMPXCHG: Test failure return",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789abcdefULL),
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BPF_LD_IMM64(R2, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_ALU64_IMM(BPF_ADD, R0, 1),
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BPF_STX_MEM(BPF_DW, R10, R1, -40),
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@ -7934,7 +7927,7 @@ static struct bpf_test tests[] = {
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"BPF_ATOMIC | BPF_DW, BPF_CMPXCHG: Test failure store",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789abcdefULL),
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BPF_LD_IMM64(R2, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_ALU64_IMM(BPF_ADD, R0, 1),
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BPF_STX_MEM(BPF_DW, R10, R1, -40),
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@ -7953,11 +7946,11 @@ static struct bpf_test tests[] = {
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"BPF_ATOMIC | BPF_DW, BPF_CMPXCHG: Test side effects",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0x0123456789abcdefULL),
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BPF_LD_IMM64(R2, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R2, 0xfedcba9876543210ULL),
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BPF_ALU64_REG(BPF_MOV, R0, R1),
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BPF_STX_MEM(BPF_DW, R10, R1, -40),
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BPF_ATOMIC_OP(BPF_DW, BPF_CMPXCHG, R10, R2, -40),
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BPF_LD_IMM64(R0, 0xfecdba9876543210ULL),
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BPF_LD_IMM64(R0, 0xfedcba9876543210ULL),
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BPF_JMP_REG(BPF_JNE, R0, R2, 1),
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BPF_ALU64_REG(BPF_SUB, R0, R2),
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BPF_EXIT_INSN(),
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