forked from Minki/linux
Merge tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.19-rc1" from Tony Lindgren: Fixes for omaps mostly to deal with dra7 timer issues and hypervisor mode. The other fixes are minor fixes for various boards. The summary of the fixes is: - Fix real-time counter rate typos for some frequencies - Fix counter frequency drift for am572x - Fix booting of secondary CPU in HYP mode - Fix n900 board name for legacy user space - Fix cpufreq in omap2plus_defconfig after Kconfig change - Fix dra7 qspi partitions And also, let's re-enable smc91x on some n900 boards that we have sitting in a few test boot systems after the boot loader dependencies got fixed. * tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Revert disabling of smc91x for n900 ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ARM: OMAP2+: Fix n900 board name for legacy user space ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode ARM: dra7xx: Fix counter frequency drift for AM572x errata i856 ARM: omap5/dra7xx: Fix frequency typos Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
e3db2217f3
@ -499,23 +499,23 @@
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};
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partition@5 {
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label = "QSPI.u-boot-spl-os";
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reg = <0x00140000 0x00010000>;
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reg = <0x00140000 0x00080000>;
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};
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partition@6 {
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label = "QSPI.u-boot-env";
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reg = <0x00150000 0x00010000>;
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reg = <0x001c0000 0x00010000>;
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};
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partition@7 {
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label = "QSPI.u-boot-env.backup1";
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reg = <0x00160000 0x0010000>;
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reg = <0x001d0000 0x0010000>;
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};
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partition@8 {
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label = "QSPI.kernel";
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reg = <0x00170000 0x0800000>;
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reg = <0x001e0000 0x0800000>;
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};
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partition@9 {
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label = "QSPI.file-system";
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reg = <0x00970000 0x01690000>;
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reg = <0x009e0000 0x01620000>;
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};
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};
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};
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@ -700,11 +700,9 @@
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};
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};
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/* Ethernet is on some early development boards and qemu */
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ethernet@gpmc {
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compatible = "smsc,lan91c94";
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status = "disabled";
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interrupt-parent = <&gpio2>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
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reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
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@ -68,7 +68,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_USERSPACE=y
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CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
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CONFIG_GENERIC_CPUFREQ_CPU0=y
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CONFIG_CPUFREQ_DT=y
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# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
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CONFIG_CPU_IDLE=y
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CONFIG_BINFMT_MISC=y
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@ -77,6 +77,24 @@ MACHINE_END
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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/* Some boards need board name for legacy userspace in /proc/cpuinfo */
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static const char *const n900_boards_compat[] __initconst = {
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"nokia,omap3-n900",
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NULL,
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};
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DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
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.reserve = omap_reserve,
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.map_io = omap3_map_io,
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.init_early = omap3430_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap3_sync32k_timer_init,
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.dt_compat = n900_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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/* Generic omap3 boards, most boards can use these */
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static const char *const omap3_boards_compat[] __initconst = {
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"ti,omap3430",
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"ti,omap3",
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@ -249,6 +249,7 @@ extern void omap4_cpu_die(unsigned int cpu);
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extern struct smp_operations omap4_smp_ops;
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extern void omap5_secondary_startup(void);
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extern void omap5_secondary_hyp_startup(void);
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#endif
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#if defined(CONFIG_SMP) && defined(CONFIG_PM)
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@ -286,6 +286,10 @@
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#define OMAP5XXX_CONTROL_STATUS 0x134
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#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
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/* DRA7XX CONTROL CORE BOOTSTRAP */
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#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
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#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
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/*
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* REVISIT: This list of registers is not comprehensive - there are more
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* that should be added.
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@ -22,6 +22,7 @@
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define AUX_CORE_BOOT0_PA 0x48281800
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#define API_HYP_ENTRY 0x102
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/*
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* OMAP5 specific entry point for secondary CPU to jump from ROM
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@ -40,6 +41,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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bne wait
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b secondary_startup
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ENDPROC(omap5_secondary_startup)
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/*
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* Same as omap5_secondary_startup except we call into the ROM to
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* enable HYP mode first. This is called instead of
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* omap5_secondary_startup if the primary CPU was put into HYP mode by
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* the boot loader.
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*/
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ENTRY(omap5_secondary_hyp_startup)
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wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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ldr r0, [r2]
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mov r0, r0, lsr #5
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne wait_2
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ldr r12, =API_HYP_ENTRY
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adr r0, hyp_boot
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smc #0
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hyp_boot:
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b secondary_startup
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ENDPROC(omap5_secondary_hyp_startup)
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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@ -22,6 +22,7 @@
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#include <linux/irqchip/arm-gic.h>
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#include <asm/smp_scu.h>
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#include <asm/virt.h>
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#include "omap-secure.h"
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#include "omap-wakeupgen.h"
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@ -227,8 +228,16 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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if (omap_secure_apis_support())
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omap_auxcoreboot_addr(virt_to_phys(startup_addr));
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else
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writel_relaxed(virt_to_phys(omap5_secondary_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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/*
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* If the boot CPU is in HYP mode then start secondary
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* CPU in HYP mode as well.
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*/
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if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
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writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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else
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writel_relaxed(virt_to_phys(omap5_secondary_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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}
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@ -54,6 +54,7 @@
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#include "soc.h"
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#include "common.h"
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#include "control.h"
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#include "powerdomain.h"
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#include "omap-secure.h"
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@ -496,7 +497,8 @@ static void __init realtime_counter_init(void)
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void __iomem *base;
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static struct clk *sys_clk;
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unsigned long rate;
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unsigned int reg, num, den;
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unsigned int reg;
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unsigned long long num, den;
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base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
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if (!base) {
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@ -511,13 +513,42 @@ static void __init realtime_counter_init(void)
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}
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rate = clk_get_rate(sys_clk);
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if (soc_is_dra7xx()) {
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/*
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* Errata i856 says the 32.768KHz crystal does not start at
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* power on, so the CPU falls back to an emulated 32KHz clock
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* based on sysclk / 610 instead. This causes the master counter
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* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
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* (OR sysclk * 75 / 244)
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*
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* This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
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* Of course any board built without a populated 32.768KHz
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* crystal would also need this fix even if the CPU is fixed
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* later.
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*
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* Either case can be detected by using the two speedselect bits
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* If they are not 0, then the 32.768KHz clock driving the
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* coarse counter that corrects the fine counter every time it
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* ticks is actually rate/610 rather than 32.768KHz and we
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* should compensate to avoid the 570ppm (at 20MHz, much worse
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* at other rates) too fast system time.
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*/
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reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
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if (reg & DRA7_SPEEDSELECT_MASK) {
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num = 75;
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den = 244;
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goto sysclk1_based;
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}
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}
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/* Numerator/denumerator values refer TRM Realtime Counter section */
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switch (rate) {
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case 1200000:
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case 12000000:
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num = 64;
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den = 125;
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break;
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case 1300000:
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case 13000000:
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num = 768;
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den = 1625;
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break;
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@ -529,11 +560,11 @@ static void __init realtime_counter_init(void)
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num = 192;
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den = 625;
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break;
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case 2600000:
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case 26000000:
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num = 384;
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den = 1625;
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break;
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case 2700000:
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case 27000000:
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num = 256;
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den = 1125;
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break;
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@ -545,6 +576,7 @@ static void __init realtime_counter_init(void)
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break;
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}
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sysclk1_based:
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/* Program numerator and denumerator registers */
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reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
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NUMERATOR_DENUMERATOR_MASK;
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@ -556,7 +588,7 @@ static void __init realtime_counter_init(void)
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reg |= den;
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writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
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arch_timer_freq = (rate / den) * num;
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arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
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set_cntfreq();
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iounmap(base);
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