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watchdog: f71808e_wdt: fix F81866 bit operation

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Fix error bit operation in watchdog_start()

Fixes: 14b24a88a3 ("watchdog: f71808e_wdt: Add F81866 support")
Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Ji-Ze Hong (Peter Hong) 2019-03-27 14:42:51 +08:00 committed by Wim Van Sebroeck
parent a3f764d2ee
commit e347afa5fb
1 changed files with 7 additions and 7 deletions
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14
drivers/watchdog/f71808e_wdt.c
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@ -339,6 +339,7 @@ static int f71862fg_pin_configure(unsigned short ioaddr)
static int watchdog_start(void) static int watchdog_start(void)
{ {
int err; int err;
u8 tmp;
/* Make sure we don't die as soon as the watchdog is enabled below */ /* Make sure we don't die as soon as the watchdog is enabled below */
err = watchdog_keepalive(); err = watchdog_keepalive();
@ -388,19 +389,18 @@ static int watchdog_start(void)
break; break;
case f81866: case f81866:
/* Set pin 70 to WDTRST# */
superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
BIT(3) | BIT(0));
superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
BIT(2));
/* /*
* GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0. * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
* The PIN 70(GPIO15/WDTRST) is controlled by 2Ch: * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
* BIT5: 0 -> WDTRST# * BIT5: 0 -> WDTRST#
* 1 -> GPIO15 * 1 -> GPIO15
*/ */
superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);
BIT(5)); tmp &= ~(BIT(3) | BIT(0));
tmp |= BIT(2);
superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
break; break;
default: default: