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drm/amdgpu/sdma3: Enable sdma wptr polling for SRIOV

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When hypervisor triggering FLR for one of VFs, need to enable sdma
wptr polling to avoid missing wptr update if enabling doorbell.

Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiangliang.Yu 2017-09-12 17:31:46 +08:00 committed by Alex Deucher
parent 19dde58929
commit e33dac39bc
1 changed files with 16 additions and 1 deletions
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17
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
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@ -641,10 +641,11 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
{ {
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
u32 rb_cntl, ib_cntl; u32 rb_cntl, ib_cntl, wptr_poll_cntl;
u32 rb_bufsz; u32 rb_bufsz;
u32 wb_offset; u32 wb_offset;
u32 doorbell; u32 doorbell;
u64 wptr_gpu_addr;
int i, j, r; int i, j, r;
for (i = 0; i < adev->sdma.num_instances; i++) { for (i = 0; i < adev->sdma.num_instances; i++) {
@ -707,6 +708,20 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
} }
WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
lower_32_bits(wptr_gpu_addr));
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
if (amdgpu_sriov_vf(adev))
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
else
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
/* enable DMA RB */ /* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);