MIPS: PNX8550: Remove support for SOC and JBS and STB810 boards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -1,43 +0,0 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* Clock module specific definitions
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*
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* Author: source@mvista.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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||||
*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
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*
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* You should have received a copy of the GNU General Public License along
|
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef __PNX8550_CM_H
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#define __PNX8550_CM_H
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#define PNX8550_CM_BASE 0xBBE47000
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#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
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#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
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#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
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#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
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// Table not complete.....
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#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
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#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
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#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
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#define PNX8550_CM_PLL_N_MASK 0x01ff0000
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#define PNX8550_CM_PLL_M_MASK 0x00003f00
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#define PNX8550_CM_PLL_P_MASK 0x0000000c
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#define PNX8550_CM_PLL_PD_MASK 0x00000002
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#endif
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@@ -1,86 +0,0 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* PNX8550 global definitions
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*
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* Author: source@mvista.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef __PNX8550_GLB_H
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#define __PNX8550_GLB_H
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#define PNX8550_GLB1_BASE 0xBBE63000
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#define PNX8550_GLB2_BASE 0xBBE4d000
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#define PNX8550_RESET_BASE 0xBBE60000
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/* PCI Inta Output Enable Registers */
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#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
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/* Bit 1:Enable DAC Powerdown
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0:DACs are enabled and are working normally
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1:DACs are powerdown
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*/
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#define PNX8550_GLB_DAC_PD 0x2
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/* Bit 0:Enable of PCI inta output
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0 = Disable PCI inta output
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1 = Enable PCI inta output
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*/
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#define PNX8550_GLB_ENABLE_INTA_O 0x1
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/* PCI Direct Mappings */
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#define PNX8550_PCIMEM 0x12000000
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#define PNX8550_PCIMEM_SIZE 0x08000000
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#define PNX8550_PCIIO 0x1c000000
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#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
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#define PNX8550_PORT_BASE KSEG1
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// GPIO def
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#define PNX8550_GPIO_BASE 0x1Be00000
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#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
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#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
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#define PNX8550_GPIO_MC_31_BIT 30
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#define PNX8550_GPIO_MC_30_BIT 28
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#define PNX8550_GPIO_MC_29_BIT 26
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#define PNX8550_GPIO_MC_28_BIT 24
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#define PNX8550_GPIO_MC_27_BIT 22
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#define PNX8550_GPIO_MC_26_BIT 20
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#define PNX8550_GPIO_MC_25_BIT 18
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#define PNX8550_GPIO_MC_24_BIT 16
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#define PNX8550_GPIO_MC_23_BIT 14
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#define PNX8550_GPIO_MC_22_BIT 12
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#define PNX8550_GPIO_MC_21_BIT 10
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#define PNX8550_GPIO_MC_20_BIT 8
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#define PNX8550_GPIO_MC_19_BIT 6
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#define PNX8550_GPIO_MC_18_BIT 4
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#define PNX8550_GPIO_MC_17_BIT 2
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#define PNX8550_GPIO_MC_16_BIT 0
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#define PNX8550_GPIO_MODE_PRIMOP 0x1
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#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
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#define PNX8550_GPIO_MODE_OPENDR 0x3
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// RESET module
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#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
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#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
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#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
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#define PNX8550_RST_REL_MIPS_RST_N 0x8
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#define PNX8550_RST_DO_SW_RST 0x4
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#define PNX8550_RST_REL_SYS_RST_OUT 0x2
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#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
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#endif
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@@ -1,140 +0,0 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* Interrupt specific definitions
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*
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* Author: source@mvista.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
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* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef __PNX8550_INT_H
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#define __PNX8550_INT_H
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#define PNX8550_GIC_BASE 0xBBE3E000
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#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
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#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
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#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
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#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
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#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
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#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
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#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
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#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
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#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
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#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
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// cp0 is two software + six hw exceptions
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#define PNX8550_INT_CP0_TOTINT 8
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#define PNX8550_INT_CP0_MIN 0
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#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
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#define MIPS_CPU_GIC_IRQ 2
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#define MIPS_CPU_TIMER_IRQ 7
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// GIC are 71 exceptions connected to cp0's first hardware exception
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#define PNX8550_INT_GIC_TOTINT 71
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#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
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#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
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#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
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#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
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#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
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#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
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#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
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#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
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#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
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#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
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#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
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#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
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#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
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#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
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#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
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#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
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#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
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#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
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#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
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#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
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#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
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#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
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#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
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#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
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#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
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#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
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#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
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#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
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#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
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#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
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#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
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#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
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#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
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#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
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#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
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#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
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#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
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#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
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#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
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#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
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#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
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#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
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#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
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#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
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#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
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#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
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#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
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#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
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#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
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#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
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#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
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#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
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#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
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#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
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#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
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#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
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#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
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#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
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#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
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#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
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#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
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#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
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#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
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#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
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#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
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#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
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#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
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#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
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#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
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#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
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#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
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#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
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#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
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// Timer are 3 exceptions connected to cp0's 7th hardware exception
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#define PNX8550_INT_TIMER_TOTINT 3
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#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
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#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
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#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
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#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
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#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
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#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
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#endif
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@@ -1,262 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
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* for more details.
|
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*
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* Copyright (C) 2005 Embedded Alley Solutions, Inc
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*/
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#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
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#define __ASM_MACH_KERNEL_ENTRY_INIT_H
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#include <asm/cacheops.h>
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#include <asm/addrspace.h>
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#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
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#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
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#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
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#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
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#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
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#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
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#define DCACHE_SET_COUNT 128 /* Data cache set count */
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#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
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#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
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.macro kernel_entry_setup
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.set push
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.set noreorder
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/*
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* PNX8550 entry point, when running a non compressed
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* kernel. When loading a zImage, the head.S code in
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* arch/mips/zboot/pnx8550 will init the caches and,
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* decompress the kernel, and branch to kernel_entry.
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*/
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cache_begin: li t0, (1<<28)
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mtc0 t0, CP0_STATUS /* cp0 usable */
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HAZARD_CP0
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mtc0 zero, CP0_CAUSE
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HAZARD_CP0
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/* Set static virtual to phys address translation and TLB disabled */
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mfc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
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mtc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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/* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
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init_icache
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nop
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init_dcache
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nop
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cachePr4450ICReset
|
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nop
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cachePr4450DCReset
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nop
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/* read ConfigPR into t0 */
|
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mfc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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|
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/* enable the TLB */
|
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or t0, (1<<19)
|
||||
|
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/* disable the ICACHE: at least 10x slower */
|
||||
/* or t0, (1<<26) */
|
||||
|
||||
/* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
|
||||
/* or t0, (1<<27) */
|
||||
|
||||
and t0, CO_CONFIGPR_VALID
|
||||
|
||||
/* enable TLB. */
|
||||
mtc0 t0, CP0_CONFIG, 7
|
||||
HAZARD_CP0
|
||||
cache_end:
|
||||
/* Setup CMEM_0 to MMIO address space, 2MB */
|
||||
lui t0, 0x1BE0
|
||||
addi t0, t0, 0x3
|
||||
mtc0 $8, $22, 4
|
||||
nop
|
||||
|
||||
/* Setup CMEM_1, 128MB */
|
||||
lui t0, 0x1000
|
||||
addi t0, t0, 0xf
|
||||
mtc0 $8, $22, 5
|
||||
nop
|
||||
|
||||
|
||||
/* Setup CMEM_2, 32MB */
|
||||
lui t0, 0x1C00
|
||||
addi t0, t0, 0xb
|
||||
mtc0 $8, $22, 6
|
||||
nop
|
||||
|
||||
/* Setup CMEM_3, 0MB */
|
||||
lui t0, 0x0
|
||||
addi t0, t0, 0x0
|
||||
mtc0 $8, $22, 7
|
||||
nop
|
||||
|
||||
/* Enable cache */
|
||||
mfc0 t0, CP0_CONFIG
|
||||
HAZARD_CP0
|
||||
and t0, t0, 0xFFFFFFF8
|
||||
or t0, t0, 3
|
||||
mtc0 t0, CP0_CONFIG
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro init_icache
|
||||
.set push
|
||||
.set noreorder
|
||||
|
||||
/* Get Cache Configuration */
|
||||
mfc0 t3, CP0_CONFIG, 1
|
||||
HAZARD_CP0
|
||||
|
||||
/* get cache Line size */
|
||||
|
||||
srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
|
||||
andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
|
||||
beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
|
||||
nop
|
||||
addiu t0, t1, 1
|
||||
ori t1, zero, 1
|
||||
sllv t1, t1, t0
|
||||
|
||||
/* get max cache Index */
|
||||
srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
|
||||
andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
|
||||
addiu t0, t2, 6
|
||||
ori t2, zero, 1
|
||||
sllv t2, t2, t0
|
||||
|
||||
/* get max cache way */
|
||||
srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
|
||||
andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
|
||||
addiu t3, t3, 1
|
||||
|
||||
/* total no of cache lines */
|
||||
multu t2, t3 /* max index * max way */
|
||||
mflo t2
|
||||
addiu t2, t2, -1
|
||||
|
||||
move t0, zero
|
||||
pr4450_next_instruction_cache_set:
|
||||
cache Index_Invalidate_I, 0(t0)
|
||||
addu t0, t0, t1 /* add bytes in a line */
|
||||
bne t2, zero, pr4450_next_instruction_cache_set
|
||||
addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
|
||||
pr4450_instr_cache_invalidated:
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro init_dcache
|
||||
.set push
|
||||
.set noreorder
|
||||
move t1, zero
|
||||
|
||||
/* Store Tag Information */
|
||||
mtc0 zero, CP0_TAGLO, 0
|
||||
HAZARD_CP0
|
||||
|
||||
mtc0 zero, CP0_TAGHI, 0
|
||||
HAZARD_CP0
|
||||
|
||||
/* Cache size is 16384 = 512 lines x 32 bytes per line */
|
||||
or t2, zero, (128*4)-1 /* 512 lines */
|
||||
/* Invalidate all lines */
|
||||
2:
|
||||
cache Index_Store_Tag_D, 0(t1)
|
||||
addiu t2, t2, -1
|
||||
bne t2, zero, 2b
|
||||
addiu t1, t1, 32 /* 32 bytes in a line */
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro cachePr4450ICReset
|
||||
.set push
|
||||
.set noreorder
|
||||
|
||||
/* Save CP0 status reg on entry; */
|
||||
/* disable interrupts during cache reset */
|
||||
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
|
||||
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
|
||||
HAZARD_CP0
|
||||
|
||||
or t1, zero, zero /* T1 = starting cache index (0) */
|
||||
ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
|
||||
|
||||
icache_invd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
|
||||
|
||||
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
|
||||
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
|
||||
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
|
||||
|
||||
/* Initialize the latches in the instruction cache tag */
|
||||
/* that drive the way selection tri-state bus drivers, by doing a */
|
||||
/* dummy load while the instruction cache is still disabled. */
|
||||
/* TODO: Is this needed ? */
|
||||
la t1, KSEG0 /* T1 = cached memory base address */
|
||||
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
|
||||
|
||||
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
.macro cachePr4450DCReset
|
||||
.set push
|
||||
.set noreorder
|
||||
mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
mtc0 zero, CP0_STATUS /* disable CPU interrupts */
|
||||
HAZARD_CP0
|
||||
|
||||
/* Writeback/invalidate entire data cache sets/ways/lines */
|
||||
or t1, zero, zero /* T1 = starting cache index (0) */
|
||||
ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
|
||||
|
||||
dcache_wbinvd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
|
||||
|
||||
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
|
||||
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
|
||||
addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
|
||||
|
||||
/* Initialize the latches in the data cache tag that drive the way
|
||||
selection tri-state bus drivers, by doing a dummy load while the
|
||||
data cache is still in the disabled mode. TODO: Is this needed ? */
|
||||
la t1, KSEG0 /* T1 = cached memory base address */
|
||||
lw zero, 0x0000(t1) /* (dummy read of first memory word) */
|
||||
|
||||
mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
|
||||
HAZARD_CP0
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
|
||||
@@ -1,121 +0,0 @@
|
||||
#ifndef __PNX8550_NAND_H
|
||||
#define __PNX8550_NAND_H
|
||||
|
||||
#define PNX8550_NAND_BASE_ADDR 0x10000000
|
||||
#define PNX8550_PCIXIO_BASE 0xBBE40000
|
||||
|
||||
#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
|
||||
#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
|
||||
#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
|
||||
#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
|
||||
#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
|
||||
#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
|
||||
#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
|
||||
#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
|
||||
#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
|
||||
#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
|
||||
#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
|
||||
#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
|
||||
#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
|
||||
#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
|
||||
#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
|
||||
#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
|
||||
|
||||
#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
|
||||
#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
|
||||
#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
|
||||
#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
|
||||
#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
|
||||
#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
|
||||
#define PNX8550_XIO_SEL0_WAIT 0x00000200
|
||||
#define PNX8550_XIO_SEL0_OFFSET 0x00000020
|
||||
#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
|
||||
#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
|
||||
#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
|
||||
#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
|
||||
#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
|
||||
#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
|
||||
#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
|
||||
#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
|
||||
#define PNX8550_XIO_SEL0_ENAB 0x00000001
|
||||
|
||||
#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
|
||||
(PNX8550_XIO_SEL0_REN_HIGH*0)| \
|
||||
(PNX8550_XIO_SEL0_REN_LOW*2) | \
|
||||
(PNX8550_XIO_SEL0_WEN_HIGH*0)| \
|
||||
(PNX8550_XIO_SEL0_WEN_LOW*2) | \
|
||||
(PNX8550_XIO_SEL0_WAIT*4) | \
|
||||
(PNX8550_XIO_SEL0_OFFSET*0) | \
|
||||
(PNX8550_XIO_SEL0_TYPE_NAND) | \
|
||||
(PNX8550_XIO_SEL0_SIZE_32MB) | \
|
||||
(PNX8550_XIO_SEL0_ENAB))
|
||||
|
||||
#define PNX8550_GPXIO_PENDING 0x00000200
|
||||
#define PNX8550_GPXIO_DONE 0x00000100
|
||||
#define PNX8550_GPXIO_CLR_DONE 0x00000080
|
||||
#define PNX8550_GPXIO_INIT 0x00000040
|
||||
#define PNX8550_GPXIO_READ_CMD 0x00000010
|
||||
#define PNX8550_GPXIO_BEN 0x0000000F
|
||||
|
||||
#define PNX8550_XIO_FLASH_64MB 0x00200000
|
||||
#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
|
||||
#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
|
||||
#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
|
||||
#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
|
||||
#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
|
||||
|
||||
#define PNX8550_XIO_INT_ACK 0x00004000
|
||||
#define PNX8550_XIO_INT_COMPL 0x00002000
|
||||
#define PNX8550_XIO_INT_NONSUP 0x00000200
|
||||
#define PNX8550_XIO_INT_ABORT 0x00000004
|
||||
|
||||
#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
|
||||
#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
|
||||
#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
|
||||
#define PNX8550_DMA_CTRL_BURST_8 0x00000000
|
||||
#define PNX8550_DMA_CTRL_BURST_16 0x00000020
|
||||
#define PNX8550_DMA_CTRL_BURST_32 0x00000040
|
||||
#define PNX8550_DMA_CTRL_BURST_64 0x00000060
|
||||
#define PNX8550_DMA_CTRL_BURST_128 0x00000080
|
||||
#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
|
||||
#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
|
||||
#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
|
||||
#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
|
||||
#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
|
||||
|
||||
/* see PCI system arch, page 100 for the full list: */
|
||||
#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
|
||||
#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
|
||||
|
||||
#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
|
||||
|
||||
#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
|
||||
|
||||
#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
|
||||
#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
|
||||
#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
|
||||
#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
|
||||
#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
|
||||
#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
|
||||
#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
|
||||
|
||||
#endif
|
||||
@@ -1,185 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PCI specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_PCI_H
|
||||
#define __PNX8550_PCI_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#define PCI_ACCESS_READ 0
|
||||
#define PCI_ACCESS_WRITE 1
|
||||
|
||||
#define PCI_CMD_IOR 0x20
|
||||
#define PCI_CMD_IOW 0x30
|
||||
#define PCI_CMD_CONFIG_READ 0xa0
|
||||
#define PCI_CMD_CONFIG_WRITE 0xb0
|
||||
|
||||
#define PCI_IO_TIMEOUT 1000
|
||||
#define PCI_IO_RETRY 5
|
||||
/* Timeout for IO and CFG accesses.
|
||||
This is in 1/1024 th of a jiffie(=10ms)
|
||||
i.e. approx 10us */
|
||||
#define PCI_IO_JIFFIES_TIMEOUT 40
|
||||
#define PCI_IO_JIFFIES_SHIFT 10
|
||||
|
||||
#define PCI_BYTE_ENABLE_MASK 0x0000000f
|
||||
#define PCI_CFG_BUS_SHIFT 16
|
||||
#define PCI_CFG_FUNC_SHIFT 8
|
||||
#define PCI_CFG_REG_SHIFT 2
|
||||
|
||||
#define PCI_BASE 0x1be00000
|
||||
#define PCI_SETUP 0x00040010
|
||||
#define PCI_DIS_REQGNT (1<<30)
|
||||
#define PCI_DIS_REQGNTA (1<<29)
|
||||
#define PCI_DIS_REQGNTB (1<<28)
|
||||
#define PCI_D2_SUPPORT (1<<27)
|
||||
#define PCI_D1_SUPPORT (1<<26)
|
||||
#define PCI_EN_TA (1<<24)
|
||||
#define PCI_EN_PCI2MMI (1<<23)
|
||||
#define PCI_EN_XIO (1<<22)
|
||||
#define PCI_BASE18_PREF (1<<21)
|
||||
#define SIZE_16M 0x3
|
||||
#define SIZE_32M 0x4
|
||||
#define SIZE_64M 0x5
|
||||
#define SIZE_128M 0x6
|
||||
#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
|
||||
#define PCI_SETUP_BASE18_EN (1<<17)
|
||||
#define PCI_SETUP_BASE14_PREF (1<<16)
|
||||
#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
|
||||
#define PCI_SETUP_BASE14_EN (1<<11)
|
||||
#define PCI_SETUP_BASE10_PREF (1<<10)
|
||||
#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
|
||||
#define PCI_SETUP_CFGMANAGE_EN (1<<1)
|
||||
#define PCI_SETUP_PCIARB_EN (1<<0)
|
||||
|
||||
#define PCI_CTRL 0x040014
|
||||
#define PCI_SWPB_DCS_PCI (1<<16)
|
||||
#define PCI_SWPB_PCI_PCI (1<<15)
|
||||
#define PCI_SWPB_PCI_DCS (1<<14)
|
||||
#define PCI_REG_WR_POST (1<<13)
|
||||
#define PCI_XIO_WR_POST (1<<12)
|
||||
#define PCI_PCI2_WR_POST (1<<13)
|
||||
#define PCI_PCI1_WR_POST (1<<12)
|
||||
#define PCI_SERR_SEEN (1<<11)
|
||||
#define PCI_B10_SPEC_RD (1<<6)
|
||||
#define PCI_B14_SPEC_RD (1<<5)
|
||||
#define PCI_B18_SPEC_RD (1<<4)
|
||||
#define PCI_B10_NOSUBWORD (1<<3)
|
||||
#define PCI_B14_NOSUBWORD (1<<2)
|
||||
#define PCI_B18_NOSUBWORD (1<<1)
|
||||
#define PCI_RETRY_TMREN (1<<0)
|
||||
|
||||
#define PCI_BASE1_LO 0x040018
|
||||
#define PCI_BASE1_HI 0x04001C
|
||||
#define PCI_BASE2_LO 0x040020
|
||||
#define PCI_BASE2_HI 0x040024
|
||||
#define PCI_RDLIFETIM 0x040028
|
||||
#define PCI_GPPM_ADDR 0x04002C
|
||||
#define PCI_GPPM_WDAT 0x040030
|
||||
#define PCI_GPPM_RDAT 0x040034
|
||||
#define PCI_GPPM_CTRL 0x040038
|
||||
#define GPPM_DONE (1<<10)
|
||||
#define INIT_PCI_CYCLE (1<<9)
|
||||
#define GPPM_CMD(X) (((X)&0xf)<<4)
|
||||
#define GPPM_BYTEEN(X) ((X)&0xf)
|
||||
#define PCI_UNLOCKREG 0x04003C
|
||||
#define UNLOCK_SSID(X) (((X)&0xff)<<8)
|
||||
#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
|
||||
#define UNLOCK_MAGIC 0xCA
|
||||
#define PCI_DEV_VEND_ID 0x040040
|
||||
#define DEVICE_ID(X) (((X)>>16)&0xffff)
|
||||
#define VENDOR_ID(X) (((X)&0xffff))
|
||||
#define PCI_CFG_CMDSTAT 0x040044
|
||||
#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
|
||||
#define PCI_CFG_COMMAND(X) ((X)&0xffff)
|
||||
#define PCI_CLASS_REV 0x040048
|
||||
#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
|
||||
#define PCI_REVID(X) ((X)&0xff)
|
||||
#define PCI_LAT_TMR 0x04004c
|
||||
#define PCI_BASE10 0x040050
|
||||
#define PCI_BASE14 0x040054
|
||||
#define PCI_BASE18 0x040058
|
||||
#define PCI_SUBSYS_ID 0x04006c
|
||||
#define PCI_CAP_PTR 0x040074
|
||||
#define PCI_CFG_MISC 0x04007c
|
||||
#define PCI_PMC 0x040080
|
||||
#define PCI_PWR_STATE 0x040084
|
||||
#define PCI_IO 0x040088
|
||||
#define PCI_SLVTUNING 0x04008C
|
||||
#define PCI_DMATUNING 0x040090
|
||||
#define PCI_DMAEADDR 0x040800
|
||||
#define PCI_DMAIADDR 0x040804
|
||||
#define PCI_DMALEN 0x040808
|
||||
#define PCI_DMACTRL 0x04080C
|
||||
#define PCI_XIOCTRL 0x040810
|
||||
#define PCI_SEL0PROF 0x040814
|
||||
#define PCI_SEL1PROF 0x040818
|
||||
#define PCI_SEL2PROF 0x04081C
|
||||
#define PCI_GPXIOADDR 0x040820
|
||||
#define PCI_NANDCTRLS 0x400830
|
||||
#define PCI_SEL3PROF 0x040834
|
||||
#define PCI_SEL4PROF 0x040838
|
||||
#define PCI_GPXIO_STAT 0x040FB0
|
||||
#define PCI_GPXIO_IMASK 0x040FB4
|
||||
#define PCI_GPXIO_ICLR 0x040FB8
|
||||
#define PCI_GPXIO_ISET 0x040FBC
|
||||
#define PCI_GPPM_STATUS 0x040FC0
|
||||
#define GPPM_DONE (1<<10)
|
||||
#define GPPM_ERR (1<<9)
|
||||
#define GPPM_MPAR_ERR (1<<8)
|
||||
#define GPPM_PAR_ERR (1<<7)
|
||||
#define GPPM_R_MABORT (1<<2)
|
||||
#define GPPM_R_TABORT (1<<1)
|
||||
#define PCI_GPPM_IMASK 0x040FC4
|
||||
#define PCI_GPPM_ICLR 0x040FC8
|
||||
#define PCI_GPPM_ISET 0x040FCC
|
||||
#define PCI_DMA_STATUS 0x040FD0
|
||||
#define PCI_DMA_IMASK 0x040FD4
|
||||
#define PCI_DMA_ICLR 0x040FD8
|
||||
#define PCI_DMA_ISET 0x040FDC
|
||||
#define PCI_ISTATUS 0x040FE0
|
||||
#define PCI_IMASK 0x040FE4
|
||||
#define PCI_ICLR 0x040FE8
|
||||
#define PCI_ISET 0x040FEC
|
||||
#define PCI_MOD_ID 0x040FFC
|
||||
|
||||
/*
|
||||
* PCI configuration cycle AD bus definition
|
||||
*/
|
||||
/* Type 0 */
|
||||
#define PCI_CFG_TYPE0_REG_SHF 0
|
||||
#define PCI_CFG_TYPE0_FUNC_SHF 8
|
||||
|
||||
/* Type 1 */
|
||||
#define PCI_CFG_TYPE1_REG_SHF 0
|
||||
#define PCI_CFG_TYPE1_FUNC_SHF 8
|
||||
#define PCI_CFG_TYPE1_DEV_SHF 11
|
||||
#define PCI_CFG_TYPE1_BUS_SHF 16
|
||||
|
||||
/*
|
||||
* Ethernet device DP83816 definition
|
||||
*/
|
||||
#define DP83816_IRQ_ETHER 66
|
||||
|
||||
#endif
|
||||
@@ -1,30 +0,0 @@
|
||||
#ifndef __IP3106_UART_H
|
||||
#define __IP3106_UART_H
|
||||
|
||||
#include <int.h>
|
||||
|
||||
/* early macros for kgdb use. fixme: clean this up */
|
||||
|
||||
#define UART_BASE 0xbbe4a000 /* PNX8550 */
|
||||
|
||||
#define PNX8550_UART_PORT0 (UART_BASE)
|
||||
#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
|
||||
|
||||
#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
|
||||
#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
|
||||
|
||||
/* early macros needed for prom/kgdb */
|
||||
|
||||
#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
|
||||
#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
|
||||
#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
|
||||
#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
|
||||
#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
|
||||
#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
|
||||
#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
|
||||
#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
|
||||
#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
|
||||
#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
|
||||
#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
|
||||
|
||||
#endif
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* USB specific definitions
|
||||
*
|
||||
* Author: source@mvista.com
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __PNX8550_USB_H
|
||||
#define __PNX8550_USB_H
|
||||
|
||||
/*
|
||||
* USB Host controller
|
||||
*/
|
||||
|
||||
#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
|
||||
#define PNX8550_USB_OHCI_OP_LEN 0x1000
|
||||
|
||||
#endif
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
|
||||
#define __ASM_MIPS_MACH_PNX8550_WAR_H
|
||||
|
||||
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
|
||||
Reference in New Issue
Block a user