forked from Minki/linux
[POWERPC] Celleb: support spu priv1 ops
SPU support routines for Celleb platform. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Ishizaki Kou
Paul Mackerras
parent
c9868fe0e0
commit
e107931956
208
arch/powerpc/platforms/celleb/spu_priv1.c
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208
arch/powerpc/platforms/celleb/spu_priv1.c
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/*
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* spu hypervisor abstraction for Beat
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/module.h>
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#include <asm/types.h>
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#include <asm/spu.h>
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#include <asm/spu_priv1.h>
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#include "beat_wrapper.h"
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static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
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{
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spu->shadow_int_mask_RW[class] = mask;
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beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
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}
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static inline u64 _int_mask_get(struct spu *spu, int class)
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{
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return spu->shadow_int_mask_RW[class];
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}
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static void int_mask_set(struct spu *spu, int class, u64 mask)
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{
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_int_mask_set(spu, class, mask);
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}
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static u64 int_mask_get(struct spu *spu, int class)
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{
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return _int_mask_get(spu, class);
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}
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static void int_mask_and(struct spu *spu, int class, u64 mask)
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{
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u64 old_mask;
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old_mask = _int_mask_get(spu, class);
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_int_mask_set(spu, class, old_mask & mask);
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}
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static void int_mask_or(struct spu *spu, int class, u64 mask)
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{
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u64 old_mask;
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old_mask = _int_mask_get(spu, class);
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_int_mask_set(spu, class, old_mask | mask);
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}
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static void int_stat_clear(struct spu *spu, int class, u64 stat)
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{
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beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
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}
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static u64 int_stat_get(struct spu *spu, int class)
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{
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u64 int_stat;
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beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
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return int_stat;
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}
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static void cpu_affinity_set(struct spu *spu, int cpu)
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{
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return;
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}
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static u64 mfc_dar_get(struct spu *spu)
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{
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u64 dar;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_dar_RW), &dar);
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return dar;
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}
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static u64 mfc_dsisr_get(struct spu *spu)
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{
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u64 dsisr;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
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return dsisr;
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}
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static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
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}
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static void mfc_sdr_setup(struct spu *spu)
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{
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return;
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}
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static void mfc_sr1_set(struct spu *spu, u64 sr1)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
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}
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static u64 mfc_sr1_get(struct spu *spu)
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{
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u64 sr1;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
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return sr1;
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}
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static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
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}
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static u64 mfc_tclass_id_get(struct spu *spu)
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{
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u64 tclass_id;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
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return tclass_id;
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}
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static void tlb_invalidate(struct spu *spu)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
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}
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static void resource_allocation_groupID_set(struct spu *spu, u64 id)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, resource_allocation_groupID_RW),
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id);
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}
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static u64 resource_allocation_groupID_get(struct spu *spu)
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{
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u64 id;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, resource_allocation_groupID_RW),
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&id);
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return id;
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}
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static void resource_allocation_enable_set(struct spu *spu, u64 enable)
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{
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beat_set_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, resource_allocation_enable_RW),
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enable);
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}
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static u64 resource_allocation_enable_get(struct spu *spu)
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{
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u64 enable;
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beat_get_spe_privileged_state_1_registers(
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spu->spe_id,
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offsetof(struct spu_priv1, resource_allocation_enable_RW),
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&enable);
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return enable;
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}
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const struct spu_priv1_ops spu_priv1_beat_ops =
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{
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.int_mask_and = int_mask_and,
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.int_mask_or = int_mask_or,
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.int_mask_set = int_mask_set,
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.int_mask_get = int_mask_get,
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.int_stat_clear = int_stat_clear,
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.int_stat_get = int_stat_get,
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.cpu_affinity_set = cpu_affinity_set,
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.mfc_dar_get = mfc_dar_get,
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.mfc_dsisr_get = mfc_dsisr_get,
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.mfc_dsisr_set = mfc_dsisr_set,
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.mfc_sdr_setup = mfc_sdr_setup,
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.mfc_sr1_set = mfc_sr1_set,
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.mfc_sr1_get = mfc_sr1_get,
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.mfc_tclass_id_set = mfc_tclass_id_set,
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.mfc_tclass_id_get = mfc_tclass_id_get,
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.tlb_invalidate = tlb_invalidate,
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.resource_allocation_groupID_set = resource_allocation_groupID_set,
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.resource_allocation_groupID_get = resource_allocation_groupID_get,
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.resource_allocation_enable_set = resource_allocation_enable_set,
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.resource_allocation_enable_get = resource_allocation_enable_get,
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};
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