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mlxsw: pci: Add more metadata fields to CQEv2

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The Completion Queue Element version 2 (CQEv2) includes various metadata
fields for packets that are mirrored / sampled to the CPU.

Add these fields so that they could be used by a later patch.

Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ido Schimmel 2021-03-14 14:19:34 +02:00 committed by David S. Miller
parent f26b30918d
commit e0eeede3d2
1 changed files with 71 additions and 0 deletions
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71
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
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@ -173,6 +173,15 @@ MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
*/
MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
#define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
/* pci_cqe_mirror_cong_high
* Congestion level in units of 8KB of the egress traffic class of the original
* packet that does mirroring to the CPU. Value of 0xFFFF means that the
* congestion level is invalid.
*/
MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
/* pci_cqe_trap_id
* Trap ID that captured the packet.
*/
@ -208,6 +217,59 @@ MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
#define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
/* pci_cqe_mirror_tclass
* The egress traffic class of the original packet that does mirroring to the
* CPU. Value of 0x1F means that the traffic class is invalid.
*/
MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
/* pci_cqe_tx_lag
* The Tx port of a packet that is mirrored / sampled to the CPU is a LAG.
*/
MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
/* pci_cqe_tx_lag_subport
* The port index within the LAG of a packet that is mirrored / sampled to the
* CPU. Reserved when tx_lag is 0.
*/
MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
#define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
#define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
/* pci_cqe_tx_lag_id
* The Tx LAG ID of the original packet that is mirrored / sampled to the CPU.
* Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
* is invalid. Reserved when tx_lag is 0.
*/
MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
/* pci_cqe_tx_system_port
* The Tx port of the original packet that is mirrored / sampled to the CPU.
* Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
* invalid. Reserved when tx_lag is 1.
*/
MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
/* pci_cqe_mirror_cong_low
* Congestion level in units of 8KB of the egress traffic class of the original
* packet that does mirroring to the CPU. Value of 0xFFFF means that the
* congestion level is invalid.
*/
MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
#define MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT 13 /* Units of 8KB. */
static inline u16 mlxsw_pci_cqe2_mirror_cong_get(const char *cqe)
{
u16 cong_high = mlxsw_pci_cqe2_mirror_cong_high_get(cqe);
u16 cong_low = mlxsw_pci_cqe2_mirror_cong_low_get(cqe);
return cong_high << 12 | cong_low;
}
/* pci_cqe_user_def_val_orig_pkt_len
* When trap_id is an ACL: User defined value from policy engine action.
*/
@ -218,6 +280,15 @@ MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
*/
MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
#define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
/* pci_cqe_mirror_latency
* End-to-end latency of the original packet that does mirroring to the CPU.
* Value of 0xFFFFFF means that the latency is invalid. Units are according to
* MOGCR.mirror_latency_units.
*/
MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
/* pci_cqe_owner
* Ownership bit.
*/