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drm/amdgpu: add sched isr to fence process

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Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
This commit is contained in:
Chunming Zhou 2015-07-21 17:43:41 +08:00 committed by Alex Deucher
parent d5fc5e82a3
commit e0d8f3c34e
1 changed files with 17 additions and 1 deletions
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18
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
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@ -346,8 +346,24 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
}
} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
if (wake)
if (wake) {
if (amdgpu_enable_scheduler) {
uint64_t handled_seq =
amd_sched_get_handled_seq(ring->scheduler);
uint64_t latest_seq =
atomic64_read(&ring->fence_drv.last_seq);
if (handled_seq == latest_seq) {
DRM_ERROR("ring %d, EOP without seq update (lastest_seq=%llu)\n",
ring->idx, latest_seq);
return;
}
do {
amd_sched_isr(ring->scheduler);
} while (amd_sched_get_handled_seq(ring->scheduler) < latest_seq);
}
wake_up_all(&ring->adev->fence_queue);
}
}
/**