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i40e/i40evf: check AQ register for valid data

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B0 Si blocks AQ registers when in Blank Flash mode - write is dropped,
read gives 0xDEADBEEF. Introduce a simple check for a correct value in one
of the AQ registers to be sure that AQ was configured correctly.
Without this check we get into an endless loop while trying to send
GetVersion AQ cmd.

Change-ID: I00102b8c5fa6c16d14289be677aafadf87f10f0d
Signed-off-by: Kamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Kamil Krawczyk 2014-04-23 04:50:02 +00:00 committed by Jeff Kirsher
parent 0d9c7ea84b
commit e03af1e1cb
2 changed files with 60 additions and 8 deletions
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34
drivers/net/ethernet/intel/i40e/i40e_adminq.c
View File

@ -291,8 +291,11 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
* *
* Configure base address and length registers for the transmit queue * Configure base address and length registers for the transmit queue
**/ **/
static void i40e_config_asq_regs(struct i40e_hw *hw) static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
{ {
i40e_status ret_code = 0;
u32 reg = 0;
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_VF_ATQBAH1, wr32(hw, I40E_VF_ATQBAH1,
@ -301,6 +304,7 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.asq.desc_buf.pa)); lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries | wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
I40E_VF_ATQLEN1_ATQENABLE_MASK)); I40E_VF_ATQLEN1_ATQENABLE_MASK));
reg = rd32(hw, I40E_VF_ATQBAL1);
} else { } else {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_PF_ATQBAH, wr32(hw, I40E_PF_ATQBAH,
@ -309,7 +313,14 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.asq.desc_buf.pa)); lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK)); I40E_PF_ATQLEN_ATQENABLE_MASK));
reg = rd32(hw, I40E_PF_ATQBAL);
} }
/* Check one register to verify that config was applied */
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
return ret_code;
} }
/** /**
@ -318,8 +329,11 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
* *
* Configure base address and length registers for the receive (event queue) * Configure base address and length registers for the receive (event queue)
**/ **/
static void i40e_config_arq_regs(struct i40e_hw *hw) static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
{ {
i40e_status ret_code = 0;
u32 reg = 0;
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_VF_ARQBAH1, wr32(hw, I40E_VF_ARQBAH1,
@ -328,6 +342,7 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.arq.desc_buf.pa)); lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries | wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
I40E_VF_ARQLEN1_ARQENABLE_MASK)); I40E_VF_ARQLEN1_ARQENABLE_MASK));
reg = rd32(hw, I40E_VF_ARQBAL1);
} else { } else {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_PF_ARQBAH, wr32(hw, I40E_PF_ARQBAH,
@ -336,10 +351,17 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.arq.desc_buf.pa)); lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK)); I40E_PF_ARQLEN_ARQENABLE_MASK));
reg = rd32(hw, I40E_PF_ARQBAL);
} }
/* Update tail in the HW to post pre-allocated buffers */ /* Update tail in the HW to post pre-allocated buffers */
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
/* Check one register to verify that config was applied */
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
return ret_code;
} }
/** /**
@ -387,7 +409,9 @@ static i40e_status i40e_init_asq(struct i40e_hw *hw)
goto init_adminq_free_rings; goto init_adminq_free_rings;
/* initialize base registers */ /* initialize base registers */
i40e_config_asq_regs(hw); ret_code = i40e_config_asq_regs(hw);
if (ret_code)
goto init_adminq_free_rings;
/* success! */ /* success! */
goto init_adminq_exit; goto init_adminq_exit;
@ -444,7 +468,9 @@ static i40e_status i40e_init_arq(struct i40e_hw *hw)
goto init_adminq_free_rings; goto init_adminq_free_rings;
/* initialize base registers */ /* initialize base registers */
i40e_config_arq_regs(hw); ret_code = i40e_config_arq_regs(hw);
if (ret_code)
goto init_adminq_free_rings;
/* success! */ /* success! */
goto init_adminq_exit; goto init_adminq_exit;

34
drivers/net/ethernet/intel/i40evf/i40e_adminq.c
View File

@ -289,8 +289,11 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
* *
* Configure base address and length registers for the transmit queue * Configure base address and length registers for the transmit queue
**/ **/
static void i40e_config_asq_regs(struct i40e_hw *hw) static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
{ {
i40e_status ret_code = 0;
u32 reg = 0;
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_VF_ATQBAH1, wr32(hw, I40E_VF_ATQBAH1,
@ -299,6 +302,7 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.asq.desc_buf.pa)); lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries | wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
I40E_VF_ATQLEN1_ATQENABLE_MASK)); I40E_VF_ATQLEN1_ATQENABLE_MASK));
reg = rd32(hw, I40E_VF_ATQBAL1);
} else { } else {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_PF_ATQBAH, wr32(hw, I40E_PF_ATQBAH,
@ -307,7 +311,14 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.asq.desc_buf.pa)); lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK)); I40E_PF_ATQLEN_ATQENABLE_MASK));
reg = rd32(hw, I40E_PF_ATQBAL);
} }
/* Check one register to verify that config was applied */
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
return ret_code;
} }
/** /**
@ -316,8 +327,11 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
* *
* Configure base address and length registers for the receive (event queue) * Configure base address and length registers for the receive (event queue)
**/ **/
static void i40e_config_arq_regs(struct i40e_hw *hw) static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
{ {
i40e_status ret_code = 0;
u32 reg = 0;
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_VF_ARQBAH1, wr32(hw, I40E_VF_ARQBAH1,
@ -326,6 +340,7 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.arq.desc_buf.pa)); lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries | wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
I40E_VF_ARQLEN1_ARQENABLE_MASK)); I40E_VF_ARQLEN1_ARQENABLE_MASK));
reg = rd32(hw, I40E_VF_ARQBAL1);
} else { } else {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_PF_ARQBAH, wr32(hw, I40E_PF_ARQBAH,
@ -334,10 +349,17 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
lower_32_bits(hw->aq.arq.desc_buf.pa)); lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK)); I40E_PF_ARQLEN_ARQENABLE_MASK));
reg = rd32(hw, I40E_PF_ARQBAL);
} }
/* Update tail in the HW to post pre-allocated buffers */ /* Update tail in the HW to post pre-allocated buffers */
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
/* Check one register to verify that config was applied */
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
return ret_code;
} }
/** /**
@ -385,7 +407,9 @@ static i40e_status i40e_init_asq(struct i40e_hw *hw)
goto init_adminq_free_rings; goto init_adminq_free_rings;
/* initialize base registers */ /* initialize base registers */
i40e_config_asq_regs(hw); ret_code = i40e_config_asq_regs(hw);
if (ret_code)
goto init_adminq_free_rings;
/* success! */ /* success! */
goto init_adminq_exit; goto init_adminq_exit;
@ -442,7 +466,9 @@ static i40e_status i40e_init_arq(struct i40e_hw *hw)
goto init_adminq_free_rings; goto init_adminq_free_rings;
/* initialize base registers */ /* initialize base registers */
i40e_config_arq_regs(hw); ret_code = i40e_config_arq_regs(hw);
if (ret_code)
goto init_adminq_free_rings;
/* success! */ /* success! */
goto init_adminq_exit; goto init_adminq_exit;