MIPS: Refactor GIC clocksource code.
Reorganize some of the GIC clocksource driver code. Below is a list of
the various changes.
* No longer select CSRC_GIC by default for Malta platform.
* Limit choice for either the GIC or R4K clocksource, not both.
* Change location in Makefile.
* Created new 'gic_read_count' function in common 'irq-gic.c' file.
* Change 'git_hpt_read' function in 'csrc-gic.c' to use new function.
* Surround GIC specific code in Malta platform code with #ifdef's.
* Only initialize the GIC clocksource if it was selected. Original
code called it unconditionally if a GIC was found.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
This commit is contained in:
committed by
Ralf Baechle
parent
28ea215186
commit
dfa762e1c3
@@ -23,11 +23,11 @@ obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
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obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
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obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
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obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
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obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
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obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
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obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
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obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
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obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
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obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
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obj-$(CONFIG_STACKTRACE) += stacktrace.o
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@@ -5,23 +5,14 @@
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/time.h>
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#include <asm/time.h>
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#include <asm/gic.h>
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static cycle_t gic_hpt_read(struct clocksource *cs)
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{
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unsigned int hi, hi2, lo;
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do {
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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return gic_read_count();
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}
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static struct clocksource gic_clocksource = {
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@@ -10,6 +10,7 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <asm/io.h>
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#include <asm/gic.h>
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@@ -32,6 +33,21 @@ static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static struct gic_pending_regs pending_regs[NR_CPUS];
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static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
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#ifdef CONFIG_CSRC_GIC
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cycle_t gic_read_count(void)
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{
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unsigned int hi, hi2, lo;
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do {
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
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} while (hi2 != hi);
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return (((cycle_t) hi) << 32) + lo;
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}
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#endif
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unsigned int gic_get_timer_pending(void)
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{
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unsigned int vpe_pending;
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