forked from Minki/linux
[ARM] mmp2: add handling on PMIC IRQ
Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs to be cleared after PMIC IRQ occured. Now append the clear operation in irq chip handler. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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@ -3,6 +3,7 @@
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struct sys_timer;
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extern void timer_init(int irq);
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extern void mmp2_clear_pmic_int(void);
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extern struct sys_timer pxa168_timer;
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extern struct sys_timer pxa910_timer;
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@ -42,6 +42,12 @@ static struct irq_chip icu_irq_chip = {
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.unmask = icu_unmask_irq,
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};
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static void pmic_irq_ack(unsigned int irq)
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{
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if (irq == IRQ_MMP2_PMIC)
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mmp2_clear_pmic_int();
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}
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#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
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static void _name_##_mask_irq(unsigned int irq) \
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{ \
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@ -82,7 +88,6 @@ SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
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static struct irq_chip _name_##_irq_chip = { \
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.name = #_name_, \
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.mask = _name_##_mask_irq, \
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.mask_ack = _name_##_mask_irq, \
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.unmask = _name_##_unmask_irq, \
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}
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@ -126,6 +131,11 @@ void __init mmp2_init_icu(void)
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}
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}
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/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
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* to be written to clear the interrupt
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*/
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pmic_irq_chip.ack = pmic_irq_ack;
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init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
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init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
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init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
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@ -37,6 +37,16 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = {
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MFP_ADDR_END,
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};
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void mmp2_clear_pmic_int(void)
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{
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unsigned long mfpr_pmic, data;
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mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
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data = __raw_readl(mfpr_pmic);
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__raw_writel(data | (1 << 6), mfpr_pmic);
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__raw_writel(data, mfpr_pmic);
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}
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static void __init mmp2_init_gpio(void)
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{
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int i;
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