iwlwifi: add support for quz firmwares
Add a new configuration with a new firmware name for quz devices. And, since these devices have the same PCI device and subsystem IDs, we need to add some code to switch from a normal qu firmware to the quz firmware. Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -82,6 +82,7 @@
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#define IWL_22000_HR_A0_FW_PRE "iwlwifi-QuQnj-a0-hr-a0-"
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#define IWL_22000_SU_Z0_FW_PRE "iwlwifi-su-z0-"
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#define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-"
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#define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-"
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#define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-"
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#define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-"
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#define IWL_22000_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-"
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@ -105,8 +106,8 @@
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IWL_22000_HR_A0_FW_PRE __stringify(api) ".ucode"
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#define IWL_22000_SU_Z0_MODULE_FIRMWARE(api) \
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IWL_22000_SU_Z0_FW_PRE __stringify(api) ".ucode"
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#define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
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IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
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IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
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IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
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#define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \
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@ -235,6 +236,18 @@ const struct iwl_cfg iwl_ax101_cfg_qu_hr = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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};
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const struct iwl_cfg iwl_ax101_cfg_quz_hr = {
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.name = "Intel(R) Wi-Fi 6 AX101",
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.fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
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IWL_DEVICE_22500,
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/*
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* This device doesn't support receiving BlockAck with a large bitmap
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* so we need to restrict the size of transmitted aggregation to the
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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};
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const struct iwl_cfg iwl_ax200_cfg_cc = {
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.name = "Intel(R) Wi-Fi 6 AX200 160MHz",
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.fw_name_pre = IWL_CC_A_FW_PRE,
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@ -444,6 +457,7 @@ MODULE_FIRMWARE(IWL_22000_HR_B_QNJ_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_22000_HR_A0_QNJ_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_22000_SU_Z0_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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MODULE_FIRMWARE(IWL_22000_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
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@ -549,6 +549,7 @@ extern const struct iwl_cfg iwl22000_2ac_cfg_hr;
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extern const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb;
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extern const struct iwl_cfg iwl22000_2ac_cfg_jf;
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extern const struct iwl_cfg iwl_ax101_cfg_qu_hr;
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extern const struct iwl_cfg iwl_ax101_cfg_quz_hr;
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extern const struct iwl_cfg iwl22000_2ax_cfg_hr;
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extern const struct iwl_cfg iwl_ax200_cfg_cc;
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extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
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@ -327,6 +327,7 @@ enum {
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#define CSR_HW_REV_TYPE_NONE (0x00001F0)
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#define CSR_HW_REV_TYPE_QNJ (0x0000360)
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#define CSR_HW_REV_TYPE_QNJ_B0 (0x0000364)
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#define CSR_HW_REV_TYPE_QUZ (0x0000354)
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#define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
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#define CSR_HW_REV_TYPE_SO (0x0000370)
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#define CSR_HW_REV_TYPE_TY (0x0000420)
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@ -3543,6 +3543,10 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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}
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} else if (cfg == &iwl_ax101_cfg_qu_hr) {
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if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
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CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) &&
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trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) {
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trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
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} else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
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CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
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trans->cfg = &iwl_ax101_cfg_qu_hr;
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} else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
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