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Merge branches 'amba', 'devel-stable', 'fixes', 'mach-types', 'mmci', 'pci' and 'versatile' into for-linus

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This commit is contained in:
Russell King 2012-05-21 15:15:10 +01:00
commit ddf90a2ff2
630 changed files with 5994 additions and 3849 deletions
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19
Documentation/ABI/testing/sysfs-bus-hsi Normal file
View File

@ -0,0 +1,19 @@
What: /sys/bus/hsi
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description:
High Speed Synchronous Serial Interface (HSI) is a
serial interface mainly used for connecting application
engines (APE) with cellular modem engines (CMT) in cellular
handsets.
The bus will be populated with devices (hsi_clients) representing
the protocols available in the system. Bus drivers implement
those protocols.
What: /sys/bus/hsi/devices/.../modalias
Date: April 2012
KernelVersion: 3.4
Contact: Carlos Chinea <carlos.chinea@nokia.com>
Description: Stores the same MODALIAS value emitted by uevent
Format: hsi:<hsi_client device name>

2
Documentation/DocBook/media/v4l/pixfmt-nv12m.xml
View File

@ -1,6 +1,6 @@
<refentry id="V4L2-PIX-FMT-NV12M">
<refmeta>
<refentrytitle>V4L2_PIX_FMT_NV12M ('NV12M')</refentrytitle>
<refentrytitle>V4L2_PIX_FMT_NV12M ('NM12')</refentrytitle>
&manvol;
</refmeta>
<refnamediv>

2
Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml
View File

@ -1,6 +1,6 @@
<refentry id="V4L2-PIX-FMT-YUV420M">
<refmeta>
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YU12M')</refentrytitle>
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YM12')</refentrytitle>
&manvol;
</refmeta>
<refnamediv>

27
Documentation/devicetree/bindings/arm/arch_timer.txt Normal file
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@ -0,0 +1,27 @@
* ARM architected timer
ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
provides per-cpu timers.
The timer is attached to a GIC to deliver its per-processor interrupts.
** Timer node properties:
- compatible : Should at least contain "arm,armv7-timer".
- interrupts : Interrupt list for secure, non-secure, virtual and
hypervisor timers, in that order.
- clock-frequency : The frequency of the main counter, in Hz. Optional.
Example:
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};

37
Documentation/power/freezing-of-tasks.txt
View File

@ -9,7 +9,7 @@ architectures).
II. How does it work?
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
PF_NOFREEZE unset (all user space processes and some kernel threads) are
regarded as 'freezable' and treated in a special way before the system enters a
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
we only consider hibernation, but the description also applies to suspend).
Namely, as the first step of the hibernation procedure the function
freeze_processes() (defined in kernel/power/process.c) is called. It executes
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
either wakes them up, if they are kernel threads, or sends fake signals to them,
if they are user space processes. A task that has TIF_FREEZE set, should react
to it by calling the function called __refrigerator() (defined in
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
Then, we say that the task is 'frozen' and therefore the set of functions
handling this mechanism is referred to as 'the freezer' (these functions are
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
User space processes are generally frozen before kernel threads.
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
whether the system is to undergo a freezing operation. And freeze_processes()
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
fake signal to all user space processes, and wakes up all the kernel threads.
All freezable tasks must react to that by calling try_to_freeze(), which
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
'frozen' and therefore the set of functions handling this mechanism is referred
to as 'the freezer' (these functions are defined in kernel/power/process.c,
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
frozen before kernel threads.
__refrigerator() must not be called directly. Instead, use the
try_to_freeze() function (defined in include/linux/freezer.h), that checks
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
flag is set.
if the task is to be frozen and makes the task enter __refrigerator().
For user space processes try_to_freeze() is called automatically from the
signal-handling code, but the freezable kernel threads need to call it
explicitly in suitable places or use the wait_event_freezable() or
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
try_to_freeze(). The main loop of a freezable kernel thread may look like the
following one:
that combine interruptible sleep with checking if the task is to be frozen and
calling try_to_freeze(). The main loop of a freezable kernel thread may look
like the following one:
set_freezable();
do {
@ -53,7 +54,7 @@ following one:
(from drivers/usb/core/hub.c::hub_thread()).
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
initiated a freezing operation, the freezing of tasks will fail and the entire
hibernation operation will be cancelled. For this reason, freezable kernel
threads must call try_to_freeze() somewhere or use one of the
wait_event_freezable() and wait_event_freezable_timeout() macros.

14
Documentation/security/keys.txt
View File

@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
The key service provides a number of features besides keys:
(*) The key service defines two special key types:
(*) The key service defines three special key types:
(+) "keyring"
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
blobs of data. These can be created, updated and read by userspace,
and aren't intended for use by kernel services.
(+) "logon"
Like a "user" key, a "logon" key has a payload that is an arbitrary
blob of data. It is intended as a place to store secrets which are
accessible to the kernel but not to userspace programs.
The description can be arbitrary, but must be prefixed with a non-zero
length string that describes the key "subclass". The subclass is
separated from the rest of the description by a ':'. "logon" keys can
be created and updated from userspace, but the payload is only
readable from kernel space.
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
process-specific keyring, and a session-specific keyring.

9
MAINTAINERS
View File

@ -2321,9 +2321,9 @@ S: Supported
F: drivers/acpi/dock.c
DOCUMENTATION
M: Randy Dunlap <rdunlap@xenotime.net>
M: Rob Landley <rob@landley.net>
L: linux-doc@vger.kernel.org
T: quilt http://xenotime.net/kernel-doc-patches/current/
T: TBD
S: Maintained
F: Documentation/
@ -3592,6 +3592,7 @@ S: Supported
F: drivers/net/wireless/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Johannes Berg <johannes.berg@intel.com>
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
@ -7578,8 +7579,8 @@ F: Documentation/filesystems/xfs.txt
F: fs/xfs/
XILINX AXI ETHERNET DRIVER
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
M: Anirudha Sarangi <anirudh@xilinx.com>
M: John Linn <John.Linn@xilinx.com>
S: Maintained
F: drivers/net/ethernet/xilinx/xilinx_axienet*

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 4
SUBLEVEL = 0
EXTRAVERSION = -rc3
EXTRAVERSION = -rc5
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*

16
arch/arm/Kconfig
View File

@ -280,6 +280,7 @@ config ARCH_INTEGRATOR
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
select MULTI_IRQ_HANDLER
help
Support for ARM's Integrator platform.
@ -1186,6 +1187,15 @@ if !MMU
source "arch/arm/Kconfig-nommu"
endif
config ARM_ERRATA_326103
bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
depends on CPU_V6
help
Executing a SWP instruction to read-only memory does not set bit 11
of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
treat the access as a read, preventing a COW from occurring and
causing the faulting task to livelock.
config ARM_ERRATA_411920
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
depends on CPU_V6 || CPU_V6K
@ -1543,6 +1553,12 @@ config HAVE_ARM_SCU
help
This option enables support for the ARM system coherency unit
config ARM_ARCH_TIMER
bool "Architected timer support"
depends on CPU_V7
help
This option enables support for the ARM architected timer
config HAVE_ARM_TWD
bool
depends on SMP

4
arch/arm/boot/dts/msm8660-surf.dts
View File

@ -10,7 +10,7 @@
intc: interrupt-controller@02080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <3>;
reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >;
};
@ -19,6 +19,6 @@
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
interrupts = <0 195 0x0>;
};
};

2
arch/arm/boot/dts/versatile-ab.dts
View File

@ -173,7 +173,7 @@
mmc@5000 {
compatible = "arm,primecell";
reg = < 0x5000 0x1000>;
interrupts = <22>;
interrupts = <22 34>;
};
kmi@6000 {
compatible = "arm,pl050", "arm,primecell";

2
arch/arm/boot/dts/versatile-pb.dts
View File

@ -41,7 +41,7 @@
mmc@b000 {
compatible = "arm,primecell";
reg = <0xb000 0x1000>;
interrupts = <23>;
interrupts = <23 34>;
};
};
};

7
arch/arm/common/it8152.c
View File

@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus,
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops it8152_ops = {
struct pci_ops it8152_ops = {
.read = it8152_pci_read_config,
.write = it8152_pci_write_config,
};
@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev)
}
struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
}
EXPORT_SYMBOL(dma_set_coherent_mask);

11
arch/arm/common/via82c505.c
View File

@ -51,7 +51,7 @@ via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where,
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops via82c505_ops = {
struct pci_ops via82c505_ops = {
.read = via82c505_read_config,
.write = via82c505_write_config,
};
@ -81,12 +81,3 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
{
return (nr == 0);
}
struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
{
if (nr == 0)
return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
&sysdata->resources);
return NULL;
}

1
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_FB=y

2
arch/arm/configs/mini2440_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_ARCH_S3C24XX=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_S3C_ADC=y
CONFIG_S3C24XX_PWM=y
CONFIG_MACH_MINI2440=y

9
arch/arm/configs/u8500_defconfig
View File

@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB5500=y
CONFIG_UX500_SOC_DB8500=y
CONFIG_MACH_HREFV60=y
CONFIG_MACH_SNOWBALL=y
CONFIG_MACH_U5500=y
@ -39,7 +37,6 @@ CONFIG_CAIF=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_MISC_DEVICES=y
CONFIG_AB8500_PWM=y
CONFIG_SENSORS_BH1780=y
CONFIG_NETDEVICES=y
@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_I2C=y
CONFIG_I2C_NOMADIK=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_TC3589X=y
CONFIG_POWER_SUPPLY=y
CONFIG_AB8500_BM=y
CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_TC3589X=y
CONFIG_AB5500_CORE=y
CONFIG_AB8500_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AB8500=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_GADGET=y

19
arch/arm/include/asm/arch_timer.h Normal file
View File

@ -0,0 +1,19 @@
#ifndef __ASMARM_ARCH_TIMER_H
#define __ASMARM_ARCH_TIMER_H
#ifdef CONFIG_ARM_ARCH_TIMER
int arch_timer_of_register(void);
int arch_timer_sched_clock_init(void);
#else
static inline int arch_timer_of_register(void)
{
return -ENXIO;
}
static inline int arch_timer_sched_clock_init(void)
{
return -ENXIO;
}
#endif
#endif

2
arch/arm/include/asm/hardware/it8152.h
View File

@ -110,6 +110,6 @@ extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
extern void it8152_init_irq(void);
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
extern struct pci_ops it8152_ops;
#endif /* __ASM_HARDWARE_IT8152_H */

17
arch/arm/include/asm/mach/pci.h
View File

@ -12,13 +12,14 @@
#define __ASM_MACH_PCI_H
struct pci_sys_data;
struct pci_ops;
struct pci_bus;
struct hw_pci {
#ifdef CONFIG_PCI_DOMAINS
int domain;
#endif
struct list_head buses;
struct pci_ops *ops;
int nr_controllers;
int (*setup)(int nr, struct pci_sys_data *);
struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
@ -45,15 +46,9 @@ struct pci_sys_data {
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
int (*map_irq)(const struct pci_dev *, u8, u8);
struct hw_pci *hw;
void *private_data; /* platform controller private data */
};
/*
* This is the standard PCI-PCI bridge swizzling algorithm.
*/
#define pci_std_swizzle pci_common_swizzle
/*
* Call this with your hw_pci struct to initialise the PCI system.
*/
@ -62,22 +57,22 @@ void pci_common_init(struct hw_pci *);
/*
* PCI controllers
*/
extern struct pci_ops iop3xx_ops;
extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
extern void iop3xx_pci_preinit(void);
extern void iop3xx_pci_preinit_cond(void);
extern struct pci_ops dc21285_ops;
extern int dc21285_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
extern void dc21285_preinit(void);
extern void dc21285_postinit(void);
extern struct pci_ops via82c505_ops;
extern int via82c505_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
extern void via82c505_init(void *sysdata);
extern struct pci_ops pci_v3_ops;
extern int pci_v3_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
extern void pci_v3_preinit(void);
extern void pci_v3_postinit(void);

7
arch/arm/include/asm/mmu.h
View File

@ -34,11 +34,4 @@ typedef struct {
#endif
/*
* switch_mm() may do a full cache flush over the context switch,
* so enable interrupts over the context switch to avoid high
* latency.
*/
#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
#endif

104
arch/arm/include/asm/mmu_context.h
View File

@ -43,45 +43,104 @@ void __check_kvm_seq(struct mm_struct *mm);
#define ASID_FIRST_VERSION (1 << ASID_BITS)
extern unsigned int cpu_last_asid;
#ifdef CONFIG_SMP
DECLARE_PER_CPU(struct mm_struct *, current_mm);
#endif
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
void __new_context(struct mm_struct *mm);
void cpu_set_reserved_ttbr0(void);
static inline void check_context(struct mm_struct *mm)
static inline void switch_new_context(struct mm_struct *mm)
{
/*
* This code is executed with interrupts enabled. Therefore,
* mm->context.id cannot be updated to the latest ASID version
* on a different CPU (and condition below not triggered)
* without first getting an IPI to reset the context. The
* alternative is to take a read_lock on mm->context.id_lock
* (after changing its type to rwlock_t).
*/
if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
__new_context(mm);
unsigned long flags;
__new_context(mm);
local_irq_save(flags);
cpu_switch_mm(mm->pgd, mm);
local_irq_restore(flags);
}
static inline void check_and_switch_context(struct mm_struct *mm,
struct task_struct *tsk)
{
if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
__check_kvm_seq(mm);
/*
* Required during context switch to avoid speculative page table
* walking with the wrong TTBR.
*/
cpu_set_reserved_ttbr0();
if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
/*
* The ASID is from the current generation, just switch to the
* new pgd. This condition is only true for calls from
* context_switch() and interrupts are already disabled.
*/
cpu_switch_mm(mm->pgd, mm);
else if (irqs_disabled())
/*
* Defer the new ASID allocation until after the context
* switch critical region since __new_context() cannot be
* called with interrupts disabled (it sends IPIs).
*/
set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
else
/*
* That is a direct call to switch_mm() or activate_mm() with
* interrupts enabled and a new context.
*/
switch_new_context(mm);
}
#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
#else
static inline void check_context(struct mm_struct *mm)
#define finish_arch_post_lock_switch \
finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
if (test_and_clear_thread_flag(TIF_SWITCH_MM))
switch_new_context(current->mm);
}
#else /* !CONFIG_CPU_HAS_ASID */
#ifdef CONFIG_MMU
static inline void check_and_switch_context(struct mm_struct *mm,
struct task_struct *tsk)
{
if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
__check_kvm_seq(mm);
#endif
if (irqs_disabled())
/*
* cpu_switch_mm() needs to flush the VIVT caches. To avoid
* high interrupt latencies, defer the call and continue
* running with the old mm. Since we only support UP systems
* on non-ASID CPUs, the old mm will remain valid until the
* finish_arch_post_lock_switch() call.
*/
set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
else
cpu_switch_mm(mm->pgd, mm);
}
#define finish_arch_post_lock_switch \
finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
struct mm_struct *mm = current->mm;
cpu_switch_mm(mm->pgd, mm);
}
}
#endif /* CONFIG_MMU */
#define init_new_context(tsk,mm) 0
#endif
#endif /* CONFIG_CPU_HAS_ASID */
#define destroy_context(mm) do { } while(0)
@ -119,12 +178,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
__flush_icache_all();
#endif
if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
#ifdef CONFIG_SMP
struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
*crt_mm = next;
#endif
check_context(next);
cpu_switch_mm(next->pgd, next);
check_and_switch_context(next, tsk);
if (cache_is_vivt())
cpumask_clear_cpu(cpu, mm_cpumask(prev));
}

8
arch/arm/include/asm/thread_info.h
View File

@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
extern void vfp_sync_hwstate(struct thread_info *);
extern void vfp_flush_hwstate(struct thread_info *);
struct user_vfp;
struct user_vfp_exc;
extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
struct user_vfp_exc __user *);
extern int vfp_restore_user_hwstate(struct user_vfp __user *,
struct user_vfp_exc __user *);
#endif
/*
@ -146,6 +153,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 20
#define TIF_SECCOMP 21
#define TIF_SWITCH_MM 22 /* deferred switch_mm */
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)

4
arch/arm/include/asm/tls.h
View File

@ -7,6 +7,8 @@
.macro set_tls_v6k, tp, tmp1, tmp2
mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
mov \tmp1, #0
mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
.endm
.macro set_tls_v6, tp, tmp1, tmp2
@ -15,6 +17,8 @@
mov \tmp2, #0xffff0fff
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
movne \tmp1, #0
mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
.endm

1
arch/arm/kernel/Makefile
View File

@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
obj-$(CONFIG_SMP) += smp.o smp_tlb.o
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o

350
arch/arm/kernel/arch_timer.c Normal file
View File

@ -0,0 +1,350 @@
/*
* linux/arch/arm/kernel/arch_timer.c
*
* Copyright (C) 2011 ARM Ltd.
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/cpu.h>
#include <linux/jiffies.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <asm/cputype.h>
#include <asm/localtimer.h>
#include <asm/arch_timer.h>
#include <asm/system_info.h>
#include <asm/sched_clock.h>
static unsigned long arch_timer_rate;
static int arch_timer_ppi;
static int arch_timer_ppi2;
static struct clock_event_device __percpu **arch_timer_evt;
/*
* Architected system timer support.
*/
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
#define ARCH_TIMER_REG_CTRL 0
#define ARCH_TIMER_REG_FREQ 1
#define ARCH_TIMER_REG_TVAL 2
static void arch_timer_reg_write(int reg, u32 val)
{
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
break;
}
isb();
}
static u32 arch_timer_reg_read(int reg)
{
u32 val;
switch (reg) {
case ARCH_TIMER_REG_CTRL:
asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
break;
case ARCH_TIMER_REG_FREQ:
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
break;
case ARCH_TIMER_REG_TVAL:
asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
break;
default:
BUG();
}
return val;
}
static irqreturn_t arch_timer_handler(int irq, void *dev_id)
{
struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
unsigned long ctrl;
ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
ctrl |= ARCH_TIMER_CTRL_IT_MASK;
arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
evt->event_handler(evt);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static void arch_timer_disable(void)
{
unsigned long ctrl;
ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
}
static void arch_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
switch (mode) {
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
arch_timer_disable();
break;
default:
break;
}
}
static int arch_timer_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long ctrl;
ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
ctrl |= ARCH_TIMER_CTRL_ENABLE;
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
return 0;
}
static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
{
/* Be safe... */
arch_timer_disable();
clk->features = CLOCK_EVT_FEAT_ONESHOT;
clk->name = "arch_sys_timer";
clk->rating = 450;
clk->set_mode = arch_timer_set_mode;
clk->set_next_event = arch_timer_set_next_event;
clk->irq = arch_timer_ppi;
clockevents_config_and_register(clk, arch_timer_rate,
0xf, 0x7fffffff);
*__this_cpu_ptr(arch_timer_evt) = clk;
enable_percpu_irq(clk->irq, 0);
if (arch_timer_ppi2)
enable_percpu_irq(arch_timer_ppi2, 0);
return 0;
}
/* Is the optional system timer available? */
static int local_timer_is_architected(void)
{
return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
}
static int arch_timer_available(void)
{
unsigned long freq;
if (!local_timer_is_architected())
return -ENXIO;
if (arch_timer_rate == 0) {
arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
/* Check the timer frequency. */
if (freq == 0) {
pr_warn("Architected timer frequency not available\n");
return -EINVAL;
}
arch_timer_rate = freq;
}
pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
return 0;
}
static inline cycle_t arch_counter_get_cntpct(void)
{
u32 cvall, cvalh;
asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
return ((cycle_t) cvalh << 32) | cvall;
}
static inline cycle_t arch_counter_get_cntvct(void)
{
u32 cvall, cvalh;
asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
return ((cycle_t) cvalh << 32) | cvall;
}
static u32 notrace arch_counter_get_cntvct32(void)
{
cycle_t cntvct = arch_counter_get_cntvct();
/*
* The sched_clock infrastructure only knows about counters
* with at most 32bits. Forget about the upper 24 bits for the
* time being...
*/
return (u32)(cntvct & (u32)~0);
}
static cycle_t arch_counter_read(struct clocksource *cs)
{
return arch_counter_get_cntpct();
}
static struct clocksource clocksource_counter = {
.name = "arch_sys_counter",
.rating = 400,
.read = arch_counter_read,
.mask = CLOCKSOURCE_MASK(56),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
{
pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
clk->irq, smp_processor_id());
disable_percpu_irq(clk->irq);
if (arch_timer_ppi2)
disable_percpu_irq(arch_timer_ppi2);
arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
}
static struct local_timer_ops arch_timer_ops __cpuinitdata = {
.setup = arch_timer_setup,
.stop = arch_timer_stop,
};
static struct clock_event_device arch_timer_global_evt;
static int __init arch_timer_register(void)
{
int err;
err = arch_timer_available();
if (err)
return err;
arch_timer_evt = alloc_percpu(struct clock_event_device *);
if (!arch_timer_evt)
return -ENOMEM;
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
"arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi, err);
goto out_free;
}
if (arch_timer_ppi2) {
err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
"arch_timer", arch_timer_evt);
if (err) {
pr_err("arch_timer: can't register interrupt %d (%d)\n",
arch_timer_ppi2, err);
arch_timer_ppi2 = 0;
goto out_free_irq;
}
}
err = local_timer_register(&arch_timer_ops);
if (err) {
/*
* We couldn't register as a local timer (could be
* because we're on a UP platform, or because some
* other local timer is already present...). Try as a
* global timer instead.
*/
arch_timer_global_evt.cpumask = cpumask_of(0);
err = arch_timer_setup(&arch_timer_global_evt);
}
if (err)
goto out_free_irq;
return 0;
out_free_irq:
free_percpu_irq(arch_timer_ppi, arch_timer_evt);
if (arch_timer_ppi2)
free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
out_free:
free_percpu(arch_timer_evt);
return err;
}
static const struct of_device_id arch_timer_of_match[] __initconst = {
{ .compatible = "arm,armv7-timer", },
{},
};
int __init arch_timer_of_register(void)
{
struct device_node *np;
u32 freq;
np = of_find_matching_node(NULL, arch_timer_of_match);
if (!np) {
pr_err("arch_timer: can't find DT node\n");
return -ENODEV;
}
/* Try to determine the frequency from the device tree or CNTFRQ */
if (!of_property_read_u32(np, "clock-frequency", &freq))
arch_timer_rate = freq;
arch_timer_ppi = irq_of_parse_and_map(np, 0);
arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
pr_info("arch_timer: found %s irqs %d %d\n",
np->name, arch_timer_ppi, arch_timer_ppi2);
return arch_timer_register();
}
int __init arch_timer_sched_clock_init(void)
{
int err;
err = arch_timer_available();
if (err)
return err;
setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
return 0;
}

37
arch/arm/kernel/bios32.c
View File

@ -374,16 +374,29 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
#endif
/*
* Swizzle the device pin each time we cross a bridge.
* This might update pin and returns the slot number.
* Swizzle the device pin each time we cross a bridge. If a platform does
* not provide a swizzle function, we perform the standard PCI swizzling.
*
* The default swizzling walks up the bus tree one level at a time, applying
* the standard swizzle function at each step, stopping when it finds the PCI
* root bus. This will return the slot number of the bridge device on the
* root bus and the interrupt pin on that device which should correspond
* with the downstream device interrupt.
*
* Platforms may override this, in which case the slot and pin returned
* depend entirely on the platform code. However, please note that the
* PCI standard swizzle is implemented on plug-in cards and Cardbus based
* PCI extenders, so it can not be ignored.
*/
static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
{
struct pci_sys_data *sys = dev->sysdata;
int slot = 0, oldpin = *pin;
int slot, oldpin = *pin;
if (sys->swizzle)
slot = sys->swizzle(dev, pin);
else
slot = pci_common_swizzle(dev, pin);
if (debug_pci)
printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
@ -410,7 +423,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
return irq;
}
static void __init pcibios_init_hw(struct hw_pci *hw)
static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
{
struct pci_sys_data *sys = NULL;
int ret;
@ -424,7 +437,6 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
#ifdef CONFIG_PCI_DOMAINS
sys->domain = hw->domain;
#endif
sys->hw = hw;
sys->busnr = busnr;
sys->swizzle = hw->swizzle;
sys->map_irq = hw->map_irq;
@ -440,14 +452,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
&iomem_resource, sys->mem_offset);
}
sys->bus = hw->scan(nr, sys);
if (hw->scan)
sys->bus = hw->scan(nr, sys);
else
sys->bus = pci_scan_root_bus(NULL, sys->busnr,
hw->ops, sys, &sys->resources);
if (!sys->bus)
panic("PCI: unable to scan bus!");
busnr = sys->bus->subordinate + 1;
list_add(&sys->node, &hw->buses);
list_add(&sys->node, head);
} else {
kfree(sys);
if (ret < 0)
@ -459,19 +475,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
void __init pci_common_init(struct hw_pci *hw)
{
struct pci_sys_data *sys;
INIT_LIST_HEAD(&hw->buses);
LIST_HEAD(head);
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
if (hw->preinit)
hw->preinit();
pcibios_init_hw(hw);
pcibios_init_hw(hw, &head);
if (hw->postinit)
hw->postinit();
pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
list_for_each_entry(sys, &hw->buses, node) {
list_for_each_entry(sys, &head, node) {
struct pci_bus *bus = sys->bus;
if (!pci_has_flag(PCI_PROBE_ONLY)) {

6
arch/arm/kernel/irq.c
View File

@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
}
c = irq_data_get_irq_chip(d);
if (c->irq_set_affinity)
c->irq_set_affinity(d, affinity, true);
else
if (!c->irq_set_affinity)
pr_debug("IRQ%u: unable to set affinity\n", d->irq);
else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
cpumask_copy(d->affinity, affinity);
return ret;
}

24
arch/arm/kernel/ptrace.c
View File

@ -906,27 +906,14 @@ long arch_ptrace(struct task_struct *child, long request,
return ret;
}
#ifdef __ARMEB__
#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
#else
#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
#endif
asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
{
unsigned long ip;
/*
* Save IP. IP is used to denote syscall entry/exit:
* IP = 0 -> entry, = 1 -> exit
*/
ip = regs->ARM_ip;
regs->ARM_ip = why;
if (!ip)
if (why)
audit_syscall_exit(regs);
else
audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0,
regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
if (!test_thread_flag(TIF_SYSCALL_TRACE))
@ -936,6 +923,13 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
current_thread_info()->syscall = scno;
/*
* IP is used to denote syscall entry/exit:
* IP = 0 -> entry, =1 -> exit
*/
ip = regs->ARM_ip;
regs->ARM_ip = why;
/* the 0x80 provides a way for the tracing parent to distinguish
between a syscall stop and SIGTRAP delivery */
ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)

55
arch/arm/kernel/signal.c
View File

@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
static int preserve_vfp_context(struct vfp_sigframe __user *frame)
{
struct thread_info *thread = current_thread_info();
struct vfp_hard_struct *h = &thread->vfpstate.hard;
const unsigned long magic = VFP_MAGIC;
const unsigned long size = VFP_STORAGE_SIZE;
int err = 0;
vfp_sync_hwstate(thread);
__put_user_error(magic, &frame->magic, err);
__put_user_error(size, &frame->size, err);
/*
* Copy the floating point registers. There can be unused
* registers see asm/hwcap.h for details.
*/
err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
sizeof(h->fpregs));
/*
* Copy the status and control register.
*/
__put_user_error(h->fpscr, &frame->ufp.fpscr, err);
if (err)
return -EFAULT;
/*
* Copy the exception registers.
*/
__put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
__put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
__put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
return err ? -EFAULT : 0;
return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
}
static int restore_vfp_context(struct vfp_sigframe __user *frame)
{
struct thread_info *thread = current_thread_info();
struct vfp_hard_struct *h = &thread->vfpstate.hard;
unsigned long magic;
unsigned long size;
unsigned long fpexc;
int err = 0;
__get_user_error(magic, &frame->magic, err);
@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
return -EINVAL;
vfp_flush_hwstate(thread);
/*
* Copy the floating point registers. There can be unused
* registers see asm/hwcap.h for details.
*/
err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
sizeof(h->fpregs));
/*
* Copy the status and control register.
*/
__get_user_error(h->fpscr, &frame->ufp.fpscr, err);
/*
* Sanitise and restore the exception registers.
*/
__get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
/* Ensure the VFP is enabled. */
fpexc |= FPEXC_EN;
/* Ensure FPINST2 is invalid and the exception flag is cleared. */
fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
h->fpexc = fpexc;
__get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
__get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
return err ? -EFAULT : 0;
return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
}
#endif

35
arch/arm/kernel/smp.c
View File

@ -251,8 +251,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
struct mm_struct *mm = &init_mm;
unsigned int cpu = smp_processor_id();
printk("CPU%u: Booted secondary processor\n", cpu);
/*
* All kernel threads share the same mm context; grab a
* reference and switch to it.
@ -264,6 +262,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
enter_lazy_tlb(mm, current);
local_flush_tlb_all();
printk("CPU%u: Booted secondary processor\n", cpu);
cpu_init();
preempt_disable();
trace_hardirqs_off();
@ -454,6 +454,9 @@ static struct local_timer_ops *lt_ops;
#ifdef CONFIG_LOCAL_TIMERS
int local_timer_register(struct local_timer_ops *ops)
{
if (!is_smp() || !setup_max_cpus)
return -ENXIO;
if (lt_ops)
return -EBUSY;
@ -510,10 +513,6 @@ static void ipi_cpu_stop(unsigned int cpu)
local_fiq_disable();
local_irq_disable();
#ifdef CONFIG_HOTPLUG_CPU
platform_cpu_kill(cpu);
#endif
while (1)
cpu_relax();
}
@ -576,17 +575,25 @@ void smp_send_reschedule(int cpu)
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
}
#ifdef CONFIG_HOTPLUG_CPU
static void smp_kill_cpus(cpumask_t *mask)
{
unsigned int cpu;
for_each_cpu(cpu, mask)
platform_cpu_kill(cpu);
}
#else
static void smp_kill_cpus(cpumask_t *mask) { }
#endif
void smp_send_stop(void)
{
unsigned long timeout;
struct cpumask mask;
if (num_online_cpus() > 1) {
struct cpumask mask;
cpumask_copy(&mask, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), &mask);
smp_cross_call(&mask, IPI_CPU_STOP);
}
cpumask_copy(&mask, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), &mask);
smp_cross_call(&mask, IPI_CPU_STOP);
/* Wait up to one second for other CPUs to stop */
timeout = USEC_PER_SEC;
@ -595,6 +602,8 @@ void smp_send_stop(void)
if (num_online_cpus() > 1)
pr_warning("SMP: failed to stop secondary CPUs\n");
smp_kill_cpus(&mask);
}
/*

6
arch/arm/kernel/smp_twd.c
View File

@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
* The twd clock events must be reprogrammed to account for the new
* frequency. The timer is local to a cpu, so cross-call to the
* changing cpu.
*
* Only wait for it to finish, if the cpu is active to avoid
* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
* booting of that cpu.
*/
if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
smp_call_function_single(freqs->cpu, twd_update_frequency,
NULL, cpu_active(freqs->cpu));
NULL, 1);
return NOTIFY_OK;
}

2
arch/arm/kernel/sys_arm.c
View File

@ -115,7 +115,7 @@ int kernel_execve(const char *filename,
"Ir" (THREAD_START_SP - sizeof(regs)),
"r" (&regs),
"Ir" (sizeof(regs))
: "r0", "r1", "r2", "r3", "ip", "lr", "memory");
: "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory");
out:
return ret;

1
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
#else
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
void __init at91_set_serial_console(unsigned portnr) {}
void __init at91_add_device_serial(void) {}

2
arch/arm/mach-at91/at91rm9200_time.c
View File

@ -23,6 +23,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <asm/mach/time.h>
@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
};
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
void __init at91rm9200_ioremap_st(u32 addr)
{

2
arch/arm/mach-at91/board-rm9200ek.c
View File

@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
};
#define EK_FLASH_BASE AT91_CHIPSELECT_0
#define EK_FLASH_SIZE SZ_2M
#define EK_FLASH_SIZE SZ_8M
static struct physmap_flash_data ek_flash_data = {
.width = 2,

5
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = {
.flags = IORESOURCE_MEM
},
[2] = {
.start = AT91_PIN_PC11,
.end = AT91_PIN_PC11,
.flags = IORESOURCE_IRQ
| IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
}
@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
static void __init ek_add_device_dm9000(void)
{
struct resource *r = &dm9000_resource[2];
/* Configure chip-select 2 (DM9000) */
sam9_smc_configure(0, 2, &dm9000_smc_config);
@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void)
/* Configure Interrupt pin as input, no pull-up */
at91_set_gpio_input(AT91_PIN_PC11, 0);
r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
platform_device_register(&dm9000_device);
}
#else

1
arch/arm/mach-at91/clock.c
View File

@ -35,6 +35,7 @@
#include "generic.h"
void __iomem *at91_pmc_base;
EXPORT_SYMBOL_GPL(at91_pmc_base);
/*
* There's a lot more which can be done with clocks, including cpufreq

2
arch/arm/mach-at91/include/mach/at91_pmc.h
View File

@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
#define at91_pmc_write(field, value) \
__raw_writel(value, at91_pmc_base + field)
#else
.extern at91_aic_base
.extern at91_pmc_base
#endif
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */

2
arch/arm/mach-at91/setup.c
View File

@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
}
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
}
void __iomem *at91_matrix_base;
EXPORT_SYMBOL_GPL(at91_matrix_base);
void __init at91_ioremap_matrix(u32 base_addr)
{

4
arch/arm/mach-bcmring/core.c
View File

@ -52,8 +52,8 @@
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>
static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
static struct clk pll1_clk = {
.name = "PLL1",

12
arch/arm/mach-cns3xxx/pcie.c
View File

@ -166,12 +166,6 @@ static struct pci_ops cns3xxx_pcie_ops = {
.write = cns3xxx_pci_write_config,
};
static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
&sys->resources);
}
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
@ -221,10 +215,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
.hw_pci = {
.domain = 0,
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
.scan = cns3xxx_pci_scan_bus,
.map_irq = cns3xxx_pcie_map_irq,
},
},
@ -264,10 +257,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
.hw_pci = {
.domain = 1,
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
.scan = cns3xxx_pci_scan_bus,
.map_irq = cns3xxx_pcie_map_irq,
},
},

24
arch/arm/mach-dove/pcie.c
View File

@ -43,6 +43,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
return 0;
pp = &pcie_port[nr];
sys->private_data = pp;
pp->root_bus_nr = sys->busnr;
/*
@ -93,19 +94,6 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
return 1;
}
static struct pcie_port *bus_to_port(int bus)
{
int i;
for (i = num_pcie_ports - 1; i >= 0; i--) {
int rbus = pcie_port[i].root_bus_nr;
if (rbus != -1 && rbus <= bus)
break;
}
return i >= 0 ? pcie_port + i : NULL;
}
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
@ -121,7 +109,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
struct pcie_port *pp = bus_to_port(bus->number);
struct pci_sys_data *sys = bus->sysdata;
struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
@ -140,7 +129,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
struct pcie_port *pp = bus_to_port(bus->number);
struct pci_sys_data *sys = bus->sysdata;
struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
@ -194,14 +184,14 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pcie_port *pp = bus_to_port(dev->bus->number);
struct pci_sys_data *sys = dev->sysdata;
struct pcie_port *pp = sys->private_data;
return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
}
static struct hw_pci dove_pci __initdata = {
.nr_controllers = 2,
.swizzle = pci_std_swizzle,
.setup = dove_pcie_setup,
.scan = dove_pcie_scan_bus,
.map_irq = dove_pcie_map_irq,

24
arch/arm/mach-exynos/clock-exynos4.c
View File

@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

24
arch/arm/mach-exynos/clock-exynos5.c
View File

@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit = (1 << 20),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "hsmmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15),
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.3",
.devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

14
arch/arm/mach-exynos/common.c
View File

@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
{
int irq;
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
#ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

13
arch/arm/mach-exynos/dev-dwmci.c
View File

@ -16,6 +16,7 @@
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mmc/dw_mmc.h>
#include <plat/devs.h>
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
}
static struct resource exynos4_dwmci_resource[] = {
[0] = {
.start = EXYNOS4_PA_DWMCI,
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
};
static struct dw_mci_board exynos4_dwci_pdata = {

1
arch/arm/mach-exynos/mach-nuri.c
View File

@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_ERASE),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};

1
arch/arm/mach-exynos/mach-universal_c210.c
View File

@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};

9
arch/arm/mach-footbridge/cats-pci.c
View File

@ -16,6 +16,11 @@
/* cats host-specific stuff */
static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin)
{
return 0;
}
static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->irq >= 255)
@ -39,11 +44,11 @@ static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
* cards being used (ie, pci-pci bridge based cards)?
*/
static struct hw_pci cats_pci __initdata = {
.swizzle = NULL,
.swizzle = cats_no_swizzle,
.map_irq = cats_map_irq,
.nr_controllers = 1,
.ops = &dc21285_ops,
.setup = dc21285_setup,
.scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};

7
arch/arm/mach-footbridge/dc21285.c
View File

@ -129,7 +129,7 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops dc21285_ops = {
struct pci_ops dc21285_ops = {
.read = dc21285_read_config,
.write = dc21285_write_config,
};
@ -284,11 +284,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
return 1;
}
struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
}
#define dc21285_request_irq(_a, _b, _c, _d, _e) \
WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)

3
arch/arm/mach-footbridge/ebsa285-pci.c
View File

@ -29,11 +29,10 @@ static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci ebsa285_pci __initdata = {
.swizzle = pci_std_swizzle,
.map_irq = ebsa285_map_irq,
.nr_controllers = 1,
.ops = &dc21285_ops,
.setup = dc21285_setup,
.scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};

3
arch/arm/mach-footbridge/netwinder-pci.c
View File

@ -43,11 +43,10 @@ static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci netwinder_pci __initdata = {
.swizzle = pci_std_swizzle,
.map_irq = netwinder_map_irq,
.nr_controllers = 1,
.ops = &dc21285_ops,
.setup = dc21285_setup,
.scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};

2
arch/arm/mach-footbridge/personal-pci.c
View File

@ -41,8 +41,8 @@ static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot,
static struct hw_pci personal_server_pci __initdata = {
.map_irq = personal_server_map_irq,
.nr_controllers = 1,
.ops = &dc21285_ops,
.setup = dc21285_setup,
.scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};

6
arch/arm/mach-imx/imx27-dt.c
View File

@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
static int __init imx27_avic_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent)
{
irq_domain_add_simple(np, 0);
irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
return 0;
}
@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
{
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
irq_domain_add_simple(np, gpio_irq_base);
gpio_irq_base -= 32;
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
NULL);
return 0;
}

2
arch/arm/mach-imx/mm-imx5.c
View File

@ -35,7 +35,7 @@ static void imx5_idle(void)
}
clk_enable(gpc_dvfs_clk);
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (tzic_enable_wake() != 0)
if (!tzic_enable_wake())
cpu_do_idle();
clk_disable(gpc_dvfs_clk);
}

39
arch/arm/mach-integrator/include/mach/entry-macro.S
View File

@ -1,39 +0,0 @@
/*
* arch/arm/mach-integrator/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for Integrator platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#include <mach/platform.h>
#include <mach/irqs.h>
.macro get_irqnr_preamble, base, tmp
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* FIXME: should not be using soo many LDRs here */
ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
mov \irqnr, #IRQ_PIC_START
ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
teq \irqstat, #0
ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
moveq \irqnr, #IRQ_CIC_START
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
.endm

63
arch/arm/mach-integrator/include/mach/irqs.h
View File

@ -22,37 +22,37 @@
/*
* Interrupt numbers
*/
#define IRQ_PIC_START 0
#define IRQ_SOFTINT 0
#define IRQ_UARTINT0 1
#define IRQ_UARTINT1 2
#define IRQ_KMIINT0 3
#define IRQ_KMIINT1 4
#define IRQ_TIMERINT0 5
#define IRQ_TIMERINT1 6
#define IRQ_TIMERINT2 7
#define IRQ_RTCINT 8
#define IRQ_AP_EXPINT0 9
#define IRQ_AP_EXPINT1 10
#define IRQ_AP_EXPINT2 11
#define IRQ_AP_EXPINT3 12
#define IRQ_AP_PCIINT0 13
#define IRQ_AP_PCIINT1 14
#define IRQ_AP_PCIINT2 15
#define IRQ_AP_PCIINT3 16
#define IRQ_AP_V3INT 17
#define IRQ_AP_CPINT0 18
#define IRQ_AP_CPINT1 19
#define IRQ_AP_LBUSTIMEOUT 20
#define IRQ_AP_APCINT 21
#define IRQ_CP_CLCDCINT 22
#define IRQ_CP_MMCIINT0 23
#define IRQ_CP_MMCIINT1 24
#define IRQ_CP_AACIINT 25
#define IRQ_CP_CPPLDINT 26
#define IRQ_CP_ETHINT 27
#define IRQ_CP_TSPENINT 28
#define IRQ_PIC_END 31
#define IRQ_PIC_START 1
#define IRQ_SOFTINT 1
#define IRQ_UARTINT0 2
#define IRQ_UARTINT1 3
#define IRQ_KMIINT0 4
#define IRQ_KMIINT1 5
#define IRQ_TIMERINT0 6
#define IRQ_TIMERINT1 7
#define IRQ_TIMERINT2 8
#define IRQ_RTCINT 9
#define IRQ_AP_EXPINT0 10
#define IRQ_AP_EXPINT1 11
#define IRQ_AP_EXPINT2 12
#define IRQ_AP_EXPINT3 13
#define IRQ_AP_PCIINT0 14
#define IRQ_AP_PCIINT1 15
#define IRQ_AP_PCIINT2 16
#define IRQ_AP_PCIINT3 17
#define IRQ_AP_V3INT 18
#define IRQ_AP_CPINT0 19
#define IRQ_AP_CPINT1 20
#define IRQ_AP_LBUSTIMEOUT 21
#define IRQ_AP_APCINT 22
#define IRQ_CP_CLCDCINT 23
#define IRQ_CP_MMCIINT0 24
#define IRQ_CP_MMCIINT1 25
#define IRQ_CP_AACIINT 26
#define IRQ_CP_CPPLDINT 27
#define IRQ_CP_ETHINT 28
#define IRQ_CP_TSPENINT 29
#define IRQ_PIC_END 29
#define IRQ_CIC_START 32
#define IRQ_CM_SOFTINT 32
@ -80,4 +80,3 @@
#define NR_IRQS_INTEGRATOR_AP 34
#define NR_IRQS_INTEGRATOR_CP 47

10
arch/arm/mach-integrator/integrator_ap.c
View File

@ -162,12 +162,6 @@ static void __init ap_map_io(void)
#define INTEGRATOR_SC_VALID_INT 0x003fffff
static struct fpga_irq_data sc_irq_data = {
.base = VA_IC_BASE,
.irq_start = 0,
.chip.name = "SC",
};
static void __init ap_init_irq(void)
{
/* Disable all interrupts initially. */
@ -178,7 +172,8 @@ static void __init ap_init_irq(void)
writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
-1, INTEGRATOR_SC_VALID_INT, NULL);
}
#ifdef CONFIG_PM
@ -478,6 +473,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
.nr_irqs = NR_IRQS_INTEGRATOR_AP,
.init_early = integrator_init_early,
.init_irq = ap_init_irq,
.handle_irq = fpga_handle_irq,
.timer = &ap_timer,
.init_machine = ap_init,
.restart = integrator_restart,

33
arch/arm/mach-integrator/integrator_cp.c
View File

@ -143,30 +143,14 @@ static void __init intcp_map_io(void)
iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}
static struct fpga_irq_data cic_irq_data = {
.base = INTCP_VA_CIC_BASE,
.irq_start = IRQ_CIC_START,
.chip.name = "CIC",
};
static struct fpga_irq_data pic_irq_data = {
.base = INTCP_VA_PIC_BASE,
.irq_start = IRQ_PIC_START,
.chip.name = "PIC",
};
static struct fpga_irq_data sic_irq_data = {
.base = INTCP_VA_SIC_BASE,
.irq_start = IRQ_SIC_START,
.chip.name = "SIC",
};
static void __init intcp_init_irq(void)
{
u32 pic_mask, sic_mask;
u32 pic_mask, cic_mask, sic_mask;
/* These masks are for the HW IRQ registers */
pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
pic_mask |= (~((~0u) << (29 - 22))) << 22;
cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
/*
@ -179,12 +163,14 @@ static void __init intcp_init_irq(void)
writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
fpga_irq_init(-1, pic_mask, &pic_irq_data);
fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
-1, pic_mask, NULL);
fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
&cic_irq_data);
fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-1, cic_mask, NULL);
fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
IRQ_CP_CPPLDINT, sic_mask, NULL);
}
/*
@ -467,6 +453,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
.nr_irqs = NR_IRQS_INTEGRATOR_CP,
.init_early = intcp_init_early,
.init_irq = intcp_init_irq,
.handle_irq = fpga_handle_irq,
.timer = &cp_timer,
.init_machine = intcp_init,
.restart = integrator_restart,

19
arch/arm/mach-integrator/pci.c
View File

@ -70,21 +70,10 @@
*/
static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
{
int pin = *pinp;
if (*pinp == 0)
*pinp = 1;
if (pin == 0)
pin = 1;
while (dev->bus->self) {
pin = pci_swizzle_interrupt_pin(dev, pin);
/*
* move up the chain of bridges, swizzling as we go.
*/
dev = dev->bus->self;
}
*pinp = pin;
return PCI_SLOT(dev->devfn);
return pci_common_swizzle(dev, pinp);
}
static int irq_tab[4] __initdata = {
@ -109,7 +98,7 @@ static struct hw_pci integrator_pci __initdata = {
.map_irq = integrator_map_irq,
.setup = pci_v3_setup,
.nr_controllers = 1,
.scan = pci_v3_scan_bus,
.ops = &pci_v3_ops,
.preinit = pci_v3_preinit,
.postinit = pci_v3_postinit,
};

8
arch/arm/mach-integrator/pci_v3.c
View File

@ -340,7 +340,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_v3_ops = {
struct pci_ops pci_v3_ops = {
.read = v3_read_config,
.write = v3_write_config,
};
@ -488,12 +488,6 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
return ret;
}
struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
&sys->resources);
}
/*
* V3_LB_BASE? - local bus address
* V3_LB_MAP? - pci bus address

1
arch/arm/mach-iop13xx/iq81340mc.c
View File

@ -54,7 +54,6 @@ iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
}
static struct hw_pci iq81340mc_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.map_irq = iq81340mc_pcix_map_irq,

1
arch/arm/mach-iop13xx/iq81340sc.c
View File

@ -56,7 +56,6 @@ iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
}
static struct hw_pci iq81340sc_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.scan = iop13xx_scan_bus,

3
arch/arm/mach-iop32x/em7210.c
View File

@ -103,11 +103,10 @@ em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci em7210_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = em7210_pci_map_irq,
};

3
arch/arm/mach-iop32x/glantank.c
View File

@ -96,11 +96,10 @@ glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci glantank_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = glantank_pci_map_irq,
};

6
arch/arm/mach-iop32x/iq31244.c
View File

@ -130,11 +130,10 @@ ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci ep80219_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = ep80219_pci_map_irq,
};
@ -166,11 +165,10 @@ iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci iq31244_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq31244_pci_map_irq,
};

3
arch/arm/mach-iop32x/iq80321.c
View File

@ -101,11 +101,10 @@ iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci iq80321_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80321_pci_map_irq,
};

3
arch/arm/mach-iop32x/n2100.c
View File

@ -114,11 +114,10 @@ n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci n2100_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
.scan = iop3xx_pci_scan_bus,
.map_irq = n2100_pci_map_irq,
};

3
arch/arm/mach-iop33x/iq80331.c
View File

@ -84,11 +84,10 @@ iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci iq80331_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80331_pci_map_irq,
};

3
arch/arm/mach-iop33x/iq80332.c
View File

@ -84,11 +84,10 @@ iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
.scan = iop3xx_pci_scan_bus,
.map_irq = iq80332_pci_map_irq,
};

9
arch/arm/mach-ixp2000/enp2611.c
View File

@ -141,13 +141,6 @@ static struct pci_ops enp2611_pci_ops = {
.write = enp2611_pci_write_config
};
static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
&sys->resources);
}
static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
@ -180,9 +173,9 @@ static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
struct hw_pci enp2611_pci __initdata = {
.nr_controllers = 1,
.ops = &enp2611_pci_ops,
.setup = enp2611_pci_setup,
.preinit = enp2611_pci_preinit,
.scan = enp2611_pci_scan_bus,
.map_irq = enp2611_pci_map_irq,
};

2
arch/arm/mach-ixp2000/include/mach/platform.h
View File

@ -127,10 +127,10 @@ unsigned long ixp2000_gettimeoffset(void);
struct pci_sys_data;
extern struct pci_ops ixp2000_pci_ops;
u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
void ixp2000_pci_preinit(void);
int ixp2000_pci_setup(int, struct pci_sys_data*);
struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);

2
arch/arm/mach-ixp2000/ixdp2400.c
View File

@ -146,10 +146,10 @@ static void ixdp2400_pci_postinit(void)
static struct hw_pci ixdp2400_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp2000_pci_ops,
.setup = ixdp2400_pci_setup,
.preinit = ixdp2400_pci_preinit,
.postinit = ixdp2400_pci_postinit,
.scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2400_pci_map_irq,
};

2
arch/arm/mach-ixp2000/ixdp2800.c
View File

@ -246,10 +246,10 @@ static void __init ixdp2800_pci_postinit(void)
struct __initdata hw_pci ixdp2800_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp2000_pci_ops,
.setup = ixdp2800_pci_setup,
.preinit = ixdp2800_pci_preinit,
.postinit = ixdp2800_pci_postinit,
.scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2800_pci_map_irq,
};

2
arch/arm/mach-ixp2000/ixdp2x01.c
View File

@ -327,9 +327,9 @@ static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
struct hw_pci ixdp2x01_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp2000_pci_ops,
.setup = ixdp2x01_pci_setup,
.preinit = ixdp2x01_pci_preinit,
.scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2x01_pci_map_irq,
};

8
arch/arm/mach-ixp2000/pci.c
View File

@ -124,17 +124,11 @@ int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
}
static struct pci_ops ixp2000_pci_ops = {
struct pci_ops ixp2000_pci_ops = {
.read = ixp2000_pci_read_config,
.write = ixp2000_pci_write_config
};
struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
{
return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
sysdata, &sysdata->resources);
}
int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{

2
arch/arm/mach-ixp23xx/include/mach/platform.h
View File

@ -37,7 +37,7 @@ void ixp23xx_sys_init(void);
void ixp23xx_restart(char, const char *);
int ixp23xx_pci_setup(int, struct pci_sys_data *);
void ixp23xx_pci_preinit(void);
struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
extern struct pci_ops ixp23xx_pci_ops;
void ixp23xx_pci_slave_init(void);
extern struct sys_timer ixp23xx_timer;

2
arch/arm/mach-ixp23xx/ixdp2351.c
View File

@ -251,9 +251,9 @@ static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci ixdp2351_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp23xx_pci_ops,
.preinit = ixp23xx_pci_preinit,
.setup = ixp23xx_pci_setup,
.scan = ixp23xx_pci_scan_bus,
.map_irq = ixdp2351_map_irq,
};

6
arch/arm/mach-ixp23xx/pci.c
View File

@ -140,12 +140,6 @@ struct pci_ops ixp23xx_pci_ops = {
.write = ixp23xx_pci_write_config,
};
struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
{
return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
sysdata, &sysdata->resources);
}
int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
volatile unsigned long temp;

2
arch/arm/mach-ixp23xx/roadrunner.c
View File

@ -118,9 +118,9 @@ static void __init roadrunner_pci_preinit(void)
static struct hw_pci roadrunner_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp23xx_pci_ops,
.preinit = roadrunner_pci_preinit,
.setup = ixp23xx_pci_setup,
.scan = ixp23xx_pci_scan_bus,
.map_irq = roadrunner_map_irq,
};

3
arch/arm/mach-ixp4xx/avila-pci.c
View File

@ -65,10 +65,9 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci avila_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = avila_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = avila_map_irq,
};

6
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -480,12 +480,6 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
return 1;
}
struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
&sys->resources);
}
int dma_set_coherent_mask(struct device *dev, u64 mask)
{
if (mask >= SZ_64M - 1)

3
arch/arm/mach-ixp4xx/coyote-pci.c
View File

@ -48,10 +48,9 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci coyote_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = coyote_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = coyote_map_irq,
};

3
arch/arm/mach-ixp4xx/dsmg600-pci.c
View File

@ -62,10 +62,9 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci __initdata dsmg600_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = dsmg600_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = dsmg600_map_irq,
};

3
arch/arm/mach-ixp4xx/fsg-pci.c
View File

@ -59,10 +59,9 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci fsg_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = fsg_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = fsg_map_irq,
};

3
arch/arm/mach-ixp4xx/gateway7001-pci.c
View File

@ -47,10 +47,9 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot,
struct hw_pci gateway7001_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = gateway7001_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = gateway7001_map_irq,
};

3
arch/arm/mach-ixp4xx/goramo_mlr.c
View File

@ -473,11 +473,10 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
static struct hw_pci gmlr_hw_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = gmlr_pci_preinit,
.postinit = gmlr_pci_postinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = gmlr_map_irq,
};

3
arch/arm/mach-ixp4xx/gtwx5715-pci.c
View File

@ -67,10 +67,9 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci gtwx5715_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = gtwx5715_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = gtwx5715_map_irq,
};

2
arch/arm/mach-ixp4xx/include/mach/platform.h
View File

@ -130,7 +130,7 @@ extern void ixp4xx_restart(char, const char *);
extern void ixp4xx_pci_preinit(void);
struct pci_sys_data;
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
extern struct pci_ops ixp4xx_ops;
/*
* GPIO-functions

3
arch/arm/mach-ixp4xx/ixdp425-pci.c
View File

@ -60,10 +60,9 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci ixdp425_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = ixdp425_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = ixdp425_map_irq,
};

3
arch/arm/mach-ixp4xx/ixdpg425-pci.c
View File

@ -42,10 +42,9 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci ixdpg425_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = ixdpg425_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = ixdpg425_map_irq,
};

3
arch/arm/mach-ixp4xx/miccpt-pci.c
View File

@ -61,10 +61,9 @@ static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci miccpt_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = miccpt_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = miccpt_map_irq,
};

3
arch/arm/mach-ixp4xx/nas100d-pci.c
View File

@ -58,10 +58,9 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci __initdata nas100d_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = nas100d_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = nas100d_map_irq,
};

3
arch/arm/mach-ixp4xx/nslu2-pci.c
View File

@ -54,10 +54,9 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci __initdata nslu2_pci = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = nslu2_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = nslu2_map_irq,
};

3
arch/arm/mach-ixp4xx/vulcan-pci.c
View File

@ -56,10 +56,9 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci vulcan_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = vulcan_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = vulcan_map_irq,
};

3
arch/arm/mach-ixp4xx/wg302v2-pci.c
View File

@ -46,10 +46,9 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
struct hw_pci wg302v2_pci __initdata = {
.nr_controllers = 1,
.ops = &ixp4xx_ops,
.preinit = wg302v2_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = wg302v2_map_irq,
};

16
arch/arm/mach-kirkwood/pcie.c
View File

@ -44,12 +44,6 @@ struct pcie_port {
static int pcie_port_map[2];
static int num_pcie_ports;
static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
{
struct pci_sys_data *sys = bus->sysdata;
return sys->private_data;
}
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
@ -79,7 +73,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
struct pcie_port *pp = bus_to_port(bus);
struct pci_sys_data *sys = bus->sysdata;
struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
@ -98,7 +93,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
struct pcie_port *pp = bus_to_port(bus);
struct pci_sys_data *sys = bus->sysdata;
struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
@ -248,13 +244,13 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
struct pcie_port *pp = bus_to_port(dev->bus);
struct pci_sys_data *sys = dev->sysdata;
struct pcie_port *pp = sys->private_data;
return pp->irq;
}
static struct hw_pci kirkwood_pci __initdata = {
.swizzle = pci_std_swizzle,
.setup = kirkwood_pcie_setup,
.scan = kirkwood_pcie_scan_bus,
.map_irq = kirkwood_pcie_map_irq,

9
arch/arm/mach-ks8695/pci.c
View File

@ -141,12 +141,6 @@ static struct pci_ops ks8695_pci_ops = {
.write = ks8695_pci_writeconfig,
};
static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
&sys->resources);
}
static struct resource pci_mem = {
.name = "PCI Memory space",
.start = KS8695_PCIMEM_PA,
@ -302,11 +296,10 @@ static void ks8695_show_pciregs(void)
static struct hw_pci ks8695_pci __initdata = {
.nr_controllers = 1,
.ops = &ks8695_pci_ops,
.preinit = ks8695_pci_preinit,
.setup = ks8695_pci_setup,
.scan = ks8695_pci_scan_bus,
.postinit = NULL,
.swizzle = pci_std_swizzle,
.map_irq = NULL,
};

25
arch/arm/mach-msm/board-msm8x60.c
View File

@ -17,6 +17,7 @@
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
msm_map_msm8x60_io();
}
#ifdef CONFIG_OF
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
{}
};
#endif
static void __init msm8x60_init_irq(void)
{
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
if (!of_have_populated_dt())
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
#ifdef CONFIG_OF
else
of_irq_init(msm_dt_gic_match);
#endif
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
{}
};
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", },
{}
};
static void __init msm8x60_dt_init(void)
{
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
GIC_SPI_START);
if (of_machine_is_compatible("qcom,msm8660-surf")) {
printk(KERN_INFO "Init surf UART registers\n");
msm8x60_init_uart12dm();

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