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drm/i915: Simplify calling engine->sync_to

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Since requests can no longer be generated as a side-effect of
intel_ring_begin(), we know that the seqno will be unchanged during
ring-emission. This predicatablity then means we do not have to check
for the seqno wrapping around whilst emitting the semaphore for
engine->sync_to().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-31-git-send-email-chris@chris-wilson.co.uk
Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-22-git-send-email-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2016-08-02 22:50:39 +01:00
parent 5b043f4e60
commit ddf07be7a2
5 changed files with 31 additions and 64 deletions
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2
drivers/gpu/drm/i915/i915_drv.h
View File

@@ -1757,7 +1757,7 @@ struct drm_i915_private {
struct i915_gem_context *kernel_context; struct i915_gem_context *kernel_context;
struct intel_engine_cs engine[I915_NUM_ENGINES]; struct intel_engine_cs engine[I915_NUM_ENGINES];
struct drm_i915_gem_object *semaphore_obj; struct drm_i915_gem_object *semaphore_obj;
uint32_t last_seqno, next_seqno; u32 next_seqno;
struct drm_dma_handle *status_page_dmah; struct drm_dma_handle *status_page_dmah;
struct resource mch_res; struct resource mch_res;

13
drivers/gpu/drm/i915/i915_gem.c
View File

@@ -2867,22 +2867,15 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
i915_gem_object_retire_request(obj, from); i915_gem_object_retire_request(obj, from);
} else { } else {
int idx = intel_engine_sync_index(from->engine, to->engine); int idx = intel_engine_sync_index(from->engine, to->engine);
u32 seqno = i915_gem_request_get_seqno(from); if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx])
if (seqno <= from->engine->semaphore.sync_seqno[idx])
return 0; return 0;
trace_i915_gem_ring_sync_to(to, from); trace_i915_gem_ring_sync_to(to, from);
ret = to->engine->semaphore.sync_to(to, from->engine, seqno); ret = to->engine->semaphore.sync_to(to, from);
if (ret) if (ret)
return ret; return ret;
/* We use last_read_req because sync_to() from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
* might have just caused seqno wrap under
* the radar.
*/
from->engine->semaphore.sync_seqno[idx] =
i915_gem_request_get_seqno(obj->last_read_req[from->engine->id]);
} }
return 0; return 0;

9
drivers/gpu/drm/i915/i915_gem_request.c
View File

@@ -264,14 +264,7 @@ int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
if (ret) if (ret)
return ret; return ret;
/* Carefully set the last_seqno value so that wrap
* detection still works
*/
dev_priv->next_seqno = seqno; dev_priv->next_seqno = seqno;
dev_priv->last_seqno = seqno - 1;
if (dev_priv->last_seqno == 0)
dev_priv->last_seqno--;
return 0; return 0;
} }
@@ -288,7 +281,7 @@ static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
dev_priv->next_seqno = 1; dev_priv->next_seqno = 1;
} }
*seqno = dev_priv->last_seqno = dev_priv->next_seqno++; *seqno = dev_priv->next_seqno++;
return 0; return 0;
} }

62
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@@ -1496,12 +1496,6 @@ static int gen8_render_emit_request(struct drm_i915_gem_request *req)
return 0; return 0;
} }
static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
u32 seqno)
{
return dev_priv->last_seqno < seqno;
}
/** /**
* intel_ring_sync - sync the waiter to the signaller on seqno * intel_ring_sync - sync the waiter to the signaller on seqno
* *
@@ -1511,24 +1505,23 @@ static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
*/ */
static int static int
gen8_ring_sync(struct drm_i915_gem_request *waiter_req, gen8_ring_sync(struct drm_i915_gem_request *wait,
struct intel_engine_cs *signaller, struct drm_i915_gem_request *signal)
u32 seqno)
{ {
struct intel_ring *waiter = waiter_req->ring; struct intel_ring *waiter = wait->ring;
struct drm_i915_private *dev_priv = waiter_req->i915; struct drm_i915_private *dev_priv = wait->i915;
u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id); u64 offset = GEN8_WAIT_OFFSET(wait->engine, signal->engine->id);
struct i915_hw_ppgtt *ppgtt; struct i915_hw_ppgtt *ppgtt;
int ret; int ret;
ret = intel_ring_begin(waiter_req, 4); ret = intel_ring_begin(wait, 4);
if (ret) if (ret)
return ret; return ret;
intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
MI_SEMAPHORE_GLOBAL_GTT | MI_SEMAPHORE_GLOBAL_GTT |
MI_SEMAPHORE_SAD_GTE_SDD); MI_SEMAPHORE_SAD_GTE_SDD);
intel_ring_emit(waiter, seqno); intel_ring_emit(waiter, signal->fence.seqno);
intel_ring_emit(waiter, lower_32_bits(offset)); intel_ring_emit(waiter, lower_32_bits(offset));
intel_ring_emit(waiter, upper_32_bits(offset)); intel_ring_emit(waiter, upper_32_bits(offset));
intel_ring_advance(waiter); intel_ring_advance(waiter);
@@ -1538,48 +1531,37 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
* We do this on the i915_switch_context() following the wait and * We do this on the i915_switch_context() following the wait and
* before the dispatch. * before the dispatch.
*/ */
ppgtt = waiter_req->ctx->ppgtt; ppgtt = wait->ctx->ppgtt;
if (ppgtt && waiter_req->engine->id != RCS) if (ppgtt && wait->engine->id != RCS)
ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); ppgtt->pd_dirty_rings |= intel_engine_flag(wait->engine);
return 0; return 0;
} }
static int static int
gen6_ring_sync(struct drm_i915_gem_request *waiter_req, gen6_ring_sync(struct drm_i915_gem_request *wait,
struct intel_engine_cs *signaller, struct drm_i915_gem_request *signal)
u32 seqno)
{ {
struct intel_ring *waiter = waiter_req->ring; struct intel_ring *waiter = wait->ring;
u32 dw1 = MI_SEMAPHORE_MBOX | u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER; MI_SEMAPHORE_REGISTER;
u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id]; u32 wait_mbox = signal->engine->semaphore.mbox.wait[wait->engine->id];
int ret; int ret;
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
ret = intel_ring_begin(wait, 4);
if (ret)
return ret;
intel_ring_emit(waiter, dw1 | wait_mbox);
/* Throughout all of the GEM code, seqno passed implies our current /* Throughout all of the GEM code, seqno passed implies our current
* seqno is >= the last seqno executed. However for hardware the * seqno is >= the last seqno executed. However for hardware the
* comparison is strictly greater than. * comparison is strictly greater than.
*/ */
seqno -= 1; intel_ring_emit(waiter, signal->fence.seqno - 1);
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
ret = intel_ring_begin(waiter_req, 4);
if (ret)
return ret;
/* If seqno wrap happened, omit the wait with no-ops */
if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
intel_ring_emit(waiter, dw1 | wait_mbox);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter, 0); intel_ring_emit(waiter, 0);
intel_ring_emit(waiter, MI_NOOP); intel_ring_emit(waiter, MI_NOOP);
} else {
intel_ring_emit(waiter, MI_NOOP);
intel_ring_emit(waiter, MI_NOOP);
intel_ring_emit(waiter, MI_NOOP);
intel_ring_emit(waiter, MI_NOOP);
}
intel_ring_advance(waiter); intel_ring_advance(waiter);
return 0; return 0;

5
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@@ -277,9 +277,8 @@ struct intel_engine_cs {
}; };
/* AKA wait() */ /* AKA wait() */
int (*sync_to)(struct drm_i915_gem_request *to_req, int (*sync_to)(struct drm_i915_gem_request *to,
struct intel_engine_cs *from, struct drm_i915_gem_request *from);
u32 seqno);
int (*signal)(struct drm_i915_gem_request *signaller_req); int (*signal)(struct drm_i915_gem_request *signaller_req);
} semaphore; } semaphore;