[ARM] S3C24A0: arch/arm/mach-s3c24a0/include/mach header files
Add initial arch/arm/mach-s3c24a0/include/mach header files for supporting Samsung S3C24A0 SoC. Signed-off-by: Sandeep Patil <sandeep.patil@azingo.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Sandeep Patil
Ben Dooks
parent
7d2dbcf9fa
commit
ddbf5654b4
115
arch/arm/mach-s3c24a0/include/mach/irqs.h
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115
arch/arm/mach-s3c24a0/include/mach/irqs.h
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/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
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*
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* Copyright (c) 2003-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_24A0_IRQS_H
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#define __ASM_ARCH_24A0_IRQS_H __FILE__
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#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
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/* for generic entry-macro.S */
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#define IRQ_EINT0 IRQ_EINT0t2
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#define IRQ_EINT3t6 S3C2410_IRQ(1)
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#define IRQ_EINT7t10 S3C2410_IRQ(2)
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#define IRQ_EINT11t14 S3C2410_IRQ(3)
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#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
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#define IRQ_TICK S3C2410_IRQ(5)
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#define IRQ_DCTQ S3C2410_IRQ(6)
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#define IRQ_MC S3C2410_IRQ(7)
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#define IRQ_ME S3C2410_IRQ(8) /* 24 */
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#define IRQ_KEYPAD S3C2410_IRQ(9)
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#define IRQ_TIMER0 S3C2410_IRQ(10)
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#define IRQ_TIMER1 S3C2410_IRQ(11)
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#define IRQ_TIMER2 S3C2410_IRQ(12)
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#define IRQ_TIMER3_4 S3C2410_IRQ(13)
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#define IRQ_OS_TIMER IRQ_TIMER3_4
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#define IRQ_LCD S3C2410_IRQ(14)
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#define IRQ_CAM_C S3C2410_IRQ(15)
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#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
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#define IRQ_UART0 S3C2410_IRQ(17)
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#define IRQ_CAM_P S3C2410_IRQ(18)
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#define IRQ_MODEM S3C2410_IRQ(19)
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#define IRQ_DMA S3C2410_IRQ(20)
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#define IRQ_SDI S3C2410_IRQ(21)
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#define IRQ_SPI0 S3C2410_IRQ(22)
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#define IRQ_UART1 S3C2410_IRQ(23)
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#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
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#define IRQ_USBD S3C2410_IRQ(25)
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#define IRQ_USBH S3C2410_IRQ(26)
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#define IRQ_IIC S3C2410_IRQ(27)
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#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
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#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
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#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
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#define IRQ_ADC_PEN S3C2410_IRQ(31)
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/* interrupts generated from the external interrupts sources */
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#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
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#define IRQ_EINT1 S3C2410_IRQ(33)
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#define IRQ_EINT2 S3C2410_IRQ(34)
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#define IRQ_EINT3 S3C2410_IRQ(35)
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#define IRQ_EINT4 S3C2410_IRQ(36)
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#define IRQ_EINT5 S3C2410_IRQ(37)
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#define IRQ_EINT6 S3C2410_IRQ(38)
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#define IRQ_EINT7 S3C2410_IRQ(39)
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#define IRQ_EINT8 S3C2410_IRQ(40)
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#define IRQ_EINT9 S3C2410_IRQ(41)
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#define IRQ_EINT10 S3C2410_IRQ(42)
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#define IRQ_EINT11 S3C2410_IRQ(43)
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#define IRQ_EINT12 S3C2410_IRQ(44)
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#define IRQ_EINT13 S3C2410_IRQ(45)
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#define IRQ_EINT14 S3C2410_IRQ(46)
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#define IRQ_EINT15 S3C2410_IRQ(47)
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#define IRQ_EINT16 S3C2410_IRQ(48)
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#define IRQ_EINT17 S3C2410_IRQ(49)
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#define IRQ_EINT18 S3C2410_IRQ(50)
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/* SUB IRQS */
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#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
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#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
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#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
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#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
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#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
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#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
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#define IRQ_S3CUART_RX2 (0x0)
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#define IRQ_S3CUART_TX2 (0x0)
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#define IRQ_S3CUART_ERR2 (0x0)
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#define IRQ_IRDA S3C2410_IRQ(57)
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#define IRQ_MSTICK S3C2410_IRQ(58)
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#define IRQ_RESERVED0 S3C2410_IRQ(59)
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#define IRQ_RESERVED1 S3C2410_IRQ(60)
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#define IRQ_RESERVED2 S3C2410_IRQ(61)
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#define IRQ_TIMER3 S3C2410_IRQ(62)
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#define IRQ_TIMER4 S3C2410_IRQ(63)
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#define IRQ_WDT S3C2410_IRQ(64)
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#define IRQ_BATFLT S3C2410_IRQ(65)
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#define IRQ_POST S3C2410_IRQ(66)
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#define IRQ_DISP_FIFO S3C2410_IRQ(67)
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#define IRQ_PENUP S3C2410_IRQ(68)
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#define IRQ_PENDN S3C2410_IRQ(69)
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#define IRQ_ADC S3C2410_IRQ(70)
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#define IRQ_DISP_FRAME S3C2410_IRQ(71)
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#define IRQ_NFLASH S3C2410_IRQ(72)
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#define IRQ_AC97 S3C2410_IRQ(73)
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#define IRQ_SPI1 S3C2410_IRQ(74)
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#define IRQ_VLX S3C2410_IRQ(75)
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#define IRQ_DMA0 S3C2410_IRQ(76)
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#define IRQ_DMA1 S3C2410_IRQ(77)
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#define IRQ_DMA2 S3C2410_IRQ(78)
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#define IRQ_DMA3 S3C2410_IRQ(79)
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#define IRQ_TC (0x0)
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#define NR_IRQS (IRQ_DMA3+1)
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#endif /* __ASM_ARCH_24A0_IRQS_H */
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78
arch/arm/mach-s3c24a0/include/mach/map.h
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78
arch/arm/mach-s3c24a0/include/mach/map.h
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/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
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*
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* Copyright 2003,2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24A0 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_24A0_MAP_H
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#define __ASM_ARCH_24A0_MAP_H __FILE__
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#define S3C24A0_PA_IO_BASE (0x40000000)
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#define S3C24A0_PA_CLKPWR (0x40000000)
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#define S3C24A0_PA_IRQ (0x40200000)
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#define S3C24A0_PA_DMA (0x40400000)
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#define S3C24A0_PA_MEMCTRL (0x40C00000)
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#define S3C24A0_PA_NAND (0x40C00000)
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#define S3C24A0_PA_SROM (0x40C20000)
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#define S3C24A0_PA_SDRAM (0x40C40000)
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#define S3C24A0_PA_BUSM (0x40CE0000)
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#define S3C24A0_PA_USBHOST (0x41000000)
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#define S3C24A0_PA_MODEMIF (0x41180000)
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#define S3C24A0_PA_IRDA (0x41800000)
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#define S3C24A0_PA_TIMER (0x44000000)
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#define S3C24A0_PA_WATCHDOG (0x44100000)
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#define S3C24A0_PA_RTC (0x44200000)
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#define S3C24A0_PA_UART (0x44400000)
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#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
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#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
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#define S3C24A0_PA_SPI (0x44500000)
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#define S3C24A0_PA_IIC (0x44600000)
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#define S3C24A0_PA_IIS (0x44700000)
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#define S3C24A0_PA_GPIO (0x44800000)
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#define S3C24A0_PA_KEYIF (0x44900000)
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#define S3C24A0_PA_USBDEV (0x44A00000)
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#define S3C24A0_PA_AC97 (0x45000000)
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#define S3C24A0_PA_ADC (0x45800000)
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#define S3C24A0_PA_SDI (0x46000000)
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#define S3C24A0_PA_MS (0x46100000)
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#define S3C24A0_PA_LCD (0x4A000000)
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#define S3C24A0_PA_VPOST (0x4A100000)
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/* physical addresses of all the chip-select areas */
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#define S3C24A0_CS0 (0x00000000)
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#define S3C24A0_CS1 (0x04000000)
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#define S3C24A0_CS2 (0x08000000)
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#define S3C24A0_CS3 (0x0C000000)
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#define S3C24A0_CS4 (0x10000000)
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#define S3C24A0_CS5 (0x40000000)
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#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
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/* Use a single interface for common resources between S3C24XX cpus */
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#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
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#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
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#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
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#define S3C24XX_PA_DMA S3C24A0_PA_DMA
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#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
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#define S3C24XX_PA_LCD S3C24A0_PA_LCD
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#define S3C24XX_PA_UART S3C24A0_PA_UART
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#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
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#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
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#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
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#define S3C24XX_PA_IIC S3C24A0_PA_IIC
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#define S3C24XX_PA_IIS S3C24A0_PA_IIS
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#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
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#define S3C24XX_PA_RTC S3C24A0_PA_RTC
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#define S3C24XX_PA_ADC S3C24A0_PA_ADC
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#define S3C24XX_PA_SPI S3C24A0_PA_SPI
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#endif /* __ASM_ARCH_24A0_MAP_H */
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19
arch/arm/mach-s3c24a0/include/mach/memory.h
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arch/arm/mach-s3c24a0/include/mach/memory.h
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/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
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* from linux/include/asm-arm/arch-rpc/memory.h
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*
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* Copyright (C) 1996,1997,1998 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_24A0_MEMORY_H
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#define __ASM_ARCH_24A0_MEMORY_H __FILE__
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#define PHYS_OFFSET UL(0x10000000)
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#endif
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88
arch/arm/mach-s3c24a0/include/mach/regs-clock.h
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arch/arm/mach-s3c24a0/include/mach/regs-clock.h
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/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
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*
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* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C24A0 clock register definitions
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*/
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#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
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#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
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#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
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#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
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#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
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#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
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#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
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/* CLKCON register bits */
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#define S3C24A0_CLKCON_VLX (1<<29)
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#define S3C24A0_CLKCON_VPOST (1<<28)
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#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
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#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
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#define S3C24A0_CLKCON_VPOSTIF (1<<25)
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#define S3C24A0_CLKCON_MPEG4IF (1<<24)
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#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
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#define S3C24A0_CLKCON_LCDC (1<<22)
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#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
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#define S3C24A0_CLKCON_MPEG4 (1<<20)
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#define S3C24A0_CLKCON_KEYPAD (1<<19)
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#define S3C24A0_CLKCON_ADC (1<<18)
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#define S3C24A0_CLKCON_SDI (1<<17)
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#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
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#define S3C24A0_CLKCON_USBD (1<<15)
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#define S3C24A0_CLKCON_GPIO (1<<14)
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#define S3C24A0_CLKCON_IIS (1<<13)
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#define S3C24A0_CLKCON_IIC (1<<12)
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#define S3C24A0_CLKCON_SPI (1<<11)
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#define S3C24A0_CLKCON_UART1 (1<<10)
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#define S3C24A0_CLKCON_UART0 (1<<9)
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#define S3C24A0_CLKCON_PWMT (1<<8)
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#define S3C24A0_CLKCON_USBH (1<<7)
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#define S3C24A0_CLKCON_AC97 (1<<6)
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#define S3C24A0_CLKCON_IrDA (1<<4)
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#define S3C24A0_CLKCON_IDLE (1<<2)
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#define S3C24A0_CLKCON_MON (1<<1)
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#define S3C24A0_CLKCON_STOP (1<<0)
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/* CLKSRC register bits */
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#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
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#define S3C24A0_CLKSRC_UPLL (1<<7)
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#define S3C24A0_CLKSRC_MPLL (1<<5)
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#define S3C24A0_CLKSRC_EXT (1<<4)
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/* Use a single interface with the common code, for s3c24xx */
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#define S3C2410_MPLLCON S3C24A0_MPLLCON
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#define S3C2410_UPLLCON S3C24A0_UPLLCON
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#define S3C2410_CLKCON S3C24A0_CLKCON
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#define S3C2410_CLKSLOW S3C24A0_CLKSRC
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#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
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#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
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#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
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#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
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#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
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#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
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#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
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#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
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#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
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#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
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#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
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#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
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#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
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#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
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#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
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#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
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#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
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#define S3C2410_CLKSLOW_SLOW (0xFF)
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#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
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#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
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25
arch/arm/mach-s3c24a0/include/mach/regs-irq.h
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arch/arm/mach-s3c24a0/include/mach/regs-irq.h
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/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
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#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
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#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
|
||||
#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
|
||||
|
||||
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
|
||||
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
|
||||
|
||||
#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user