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drm/amdgpu/pm: mark pcie link/speed arrays as const

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Noticed-by: Dave Airlie <airlied@linux.ie>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2021-03-23 23:48:49 -04:00
parent 266b2d25e3
commit dd67d7a620
4 changed files with 8 additions and 8 deletions
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4
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
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@@ -61,8 +61,8 @@
#define LINK_WIDTH_MAX 6 #define LINK_WIDTH_MAX 6
#define LINK_SPEED_MAX 3 #define LINK_SPEED_MAX 3
static __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16}; static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
static __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160}; static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
static const static const
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =

4
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
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@@ -52,8 +52,8 @@
#define LINK_WIDTH_MAX 6 #define LINK_WIDTH_MAX 6
#define LINK_SPEED_MAX 3 #define LINK_SPEED_MAX 3
static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160}; static const int link_speed[] = {25, 50, 80, 160};
static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask); enum pp_clock_type type, uint32_t mask);

4
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
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@@ -57,8 +57,8 @@
#define LINK_WIDTH_MAX 6 #define LINK_WIDTH_MAX 6
#define LINK_SPEED_MAX 3 #define LINK_SPEED_MAX 3
static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160}; static const int link_speed[] = {25, 50, 80, 160};
static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
{ {

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
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@@ -72,8 +72,8 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160}; static const int link_speed[] = {25, 50, 80, 160};
int smu_v13_0_init_microcode(struct smu_context *smu) int smu_v13_0_init_microcode(struct smu_context *smu)
{ {