arm64: dts: hisilicon: hi3670: Add UART nodes
Add UART nodes for HiSilicon HI3670 SoC and also relevant pinmux/pinconf entries. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Manivannan Sadhasivam
Wei Xu
parent
e18813021a
commit
dd54bb8a0a
@ -187,6 +187,76 @@
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#clock-cells = <1>;
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};
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uart0: serial@fdf02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf02000 0x0 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
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status = "disabled";
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};
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uart1: serial@fdf00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf00000 0x0 0x1000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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status = "disabled";
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};
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uart2: serial@fdf03000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf03000 0x0 0x1000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
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status = "disabled";
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};
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uart3: serial@ffd74000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xffd74000 0x0 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
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status = "disabled";
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};
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uart4: serial@fdf01000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf01000 0x0 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
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status = "disabled";
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};
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uart5: serial@fdf05000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf05000 0x0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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status = "disabled";
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};
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uart6: serial@fff32000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfff32000 0x0 0x1000>;
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@ -194,6 +264,8 @@
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clocks = <&crg_ctrl HI3670_CLK_UART6>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
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status = "disabled";
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};
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@ -20,6 +20,47 @@
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pinctrl-single,function-mask = <0x7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 82 0>;
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uart0_pmx_func: uart0_pmx_func {
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pinctrl-single,pins = <
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0x054 MUX_M2 /* UART0_RXD */
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0x058 MUX_M2 /* UART0_TXD */
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>;
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};
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uart2_pmx_func: uart2_pmx_func {
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pinctrl-single,pins = <
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0x700 MUX_M2 /* UART2_CTS_N */
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0x704 MUX_M2 /* UART2_RTS_N */
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0x708 MUX_M2 /* UART2_RXD */
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0x70c MUX_M2 /* UART2_TXD */
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>;
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};
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uart3_pmx_func: uart3_pmx_func {
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pinctrl-single,pins = <
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0x064 MUX_M1 /* UART3_CTS_N */
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0x068 MUX_M1 /* UART3_RTS_N */
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0x06c MUX_M1 /* UART3_RXD */
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0x070 MUX_M1 /* UART3_TXD */
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>;
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};
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uart4_pmx_func: uart4_pmx_func {
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pinctrl-single,pins = <
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0x074 MUX_M1 /* UART4_CTS_N */
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0x078 MUX_M1 /* UART4_RTS_N */
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0x07c MUX_M1 /* UART4_RXD */
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0x080 MUX_M1 /* UART4_TXD */
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>;
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};
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uart6_pmx_func: uart6_pmx_func {
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pinctrl-single,pins = <
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0x05c MUX_M1 /* UART6_RXD */
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0x060 MUX_M1 /* UART6_TXD */
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>;
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};
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};
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pmx2: pinmux@e896c800 {
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@ -27,6 +68,122 @@
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reg = <0x0 0xe896c800 0x0 0x72c>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <0x20>;
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uart0_cfg_func: uart0_cfg_func {
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pinctrl-single,pins = <
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0x058 0x0 /* UART0_RXD */
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0x05c 0x0 /* UART0_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart2_cfg_func: uart2_cfg_func {
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pinctrl-single,pins = <
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0x700 0x0 /* UART2_CTS_N */
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0x704 0x0 /* UART2_RTS_N */
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0x708 0x0 /* UART2_RXD */
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0x70c 0x0 /* UART2_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart3_cfg_func: uart3_cfg_func {
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pinctrl-single,pins = <
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0x068 0x0 /* UART3_CTS_N */
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0x06c 0x0 /* UART3_RTS_N */
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0x070 0x0 /* UART3_RXD */
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0x074 0x0 /* UART3_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart4_cfg_func: uart4_cfg_func {
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pinctrl-single,pins = <
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0x078 0x0 /* UART4_CTS_N */
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0x07c 0x0 /* UART4_RTS_N */
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0x080 0x0 /* UART4_RXD */
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0x084 0x0 /* UART4_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_04MA DRIVE6_MASK
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>;
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};
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uart6_cfg_func: uart6_cfg_func {
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pinctrl-single,pins = <
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0x060 0x0 /* UART6_RXD */
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0x064 0x0 /* UART6_TXD */
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>;
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pinctrl-single,bias-pulldown = <
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PULL_DIS
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PULL_DOWN
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PULL_DIS
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PULL_DOWN
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>;
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pinctrl-single,bias-pullup = <
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PULL_DIS
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PULL_UP
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PULL_DIS
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_02MA DRIVE6_MASK
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>;
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};
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};
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pmx5: pinmux@fc182000 {
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