qla4xxx: qla4xxx: Move qla4_8xxx_ms_mem_write_128b to ql4_nx.c
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Vikas Chaudhary
Christoph Hellwig
parent
3c3cab1727
commit
dd3b854e16
@ -249,112 +249,6 @@ void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha)
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qla4_83xx_flash_unlock(ha);
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}
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/**
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* qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
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* @ha: Pointer to adapter structure
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* @addr: Flash address to write to
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* @data: Data to be written
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* @count: word_count to be written
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*
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* Return: On success return QLA_SUCCESS
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* On error return QLA_ERROR
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**/
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int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
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uint32_t *data, uint32_t count)
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{
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int i, j;
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uint32_t agt_ctrl;
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unsigned long flags;
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int ret_val = QLA_SUCCESS;
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/* Only 128-bit aligned access */
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if (addr & 0xF) {
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write;
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}
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write_lock_irqsave(&ha->hw_lock, flags);
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/* Write address */
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ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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for (i = 0; i < count; i++, addr += 16) {
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if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
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QLA8XXX_ADDR_QDR_NET_MAX)) ||
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(QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
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QLA8XXX_ADDR_DDR_NET_MAX)))) {
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write_unlock;
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}
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ret_val = ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_ADDR_LO,
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addr);
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/* Write data */
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_LO,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_HI,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_ULO,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_UHI,
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*data++);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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/* Check write status */
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ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
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MIU_TA_CTL_WRITE_ENABLE);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_CTRL,
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MIU_TA_CTL_WRITE_START);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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ret_val = ha->isp_ops->rd_reg_indirect(ha,
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MD_MIU_TEST_AGT_CTRL,
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&agt_ctrl);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
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break;
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}
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/* Status check failed */
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if (j >= MAX_CTL_CHECK) {
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printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
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__func__);
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write_unlock;
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}
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}
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exit_ms_mem_write_unlock:
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write_unlock_irqrestore(&ha->hw_lock, flags);
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exit_ms_mem_write:
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return ret_val;
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}
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#define INTENT_TO_RECOVER 0x01
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#define PROCEED_TO_RECOVER 0x02
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@ -1177,6 +1177,112 @@ qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
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return 0;
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}
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/**
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* qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
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* @ha: Pointer to adapter structure
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* @addr: Flash address to write to
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* @data: Data to be written
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* @count: word_count to be written
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*
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* Return: On success return QLA_SUCCESS
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* On error return QLA_ERROR
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**/
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int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
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uint32_t *data, uint32_t count)
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{
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int i, j;
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uint32_t agt_ctrl;
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unsigned long flags;
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int ret_val = QLA_SUCCESS;
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/* Only 128-bit aligned access */
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if (addr & 0xF) {
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write;
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}
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write_lock_irqsave(&ha->hw_lock, flags);
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/* Write address */
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ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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for (i = 0; i < count; i++, addr += 16) {
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if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
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QLA8XXX_ADDR_QDR_NET_MAX)) ||
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(QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
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QLA8XXX_ADDR_DDR_NET_MAX)))) {
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write_unlock;
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}
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ret_val = ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_ADDR_LO,
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addr);
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/* Write data */
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_LO,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_HI,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_ULO,
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*data++);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_WRDATA_UHI,
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*data++);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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/* Check write status */
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ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
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MIU_TA_CTL_WRITE_ENABLE);
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ret_val |= ha->isp_ops->wr_reg_indirect(ha,
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MD_MIU_TEST_AGT_CTRL,
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MIU_TA_CTL_WRITE_START);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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for (j = 0; j < MAX_CTL_CHECK; j++) {
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ret_val = ha->isp_ops->rd_reg_indirect(ha,
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MD_MIU_TEST_AGT_CTRL,
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&agt_ctrl);
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if (ret_val == QLA_ERROR) {
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ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
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__func__);
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goto exit_ms_mem_write_unlock;
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}
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if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
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break;
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}
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/* Status check failed */
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if (j >= MAX_CTL_CHECK) {
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printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
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__func__);
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ret_val = QLA_ERROR;
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goto exit_ms_mem_write_unlock;
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}
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}
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exit_ms_mem_write_unlock:
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write_unlock_irqrestore(&ha->hw_lock, flags);
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exit_ms_mem_write:
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return ret_val;
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}
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static int
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qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
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{
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