forked from Minki/linux
drm/msm/dsi: Add support for msm8x94
DSI controller on msm8x94 is version 1.3, which requires different power supplies and works with 20nm DSI PHY. This change is to add the basic support for this version. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -47,6 +47,7 @@ Required properties:
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- compatible: Could be the following
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* "qcom,dsi-phy-28nm-hpm"
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* "qcom,dsi-phy-28nm-lp"
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* "qcom,dsi-phy-20nm"
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- reg: Physical base address and length of the registers of PLL, PHY and PHY
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regulator
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- reg-names: The names of register regions. The following regions are required:
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@ -62,6 +63,10 @@ Required properties:
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* "iface_clk"
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- vddio-supply: phandle to vdd-io regulator device node
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Optional properties:
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- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
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regulator is wanted.
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Example:
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mdss_dsi0: qcom,mdss_dsi@fd922800 {
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compatible = "qcom,mdss-dsi-ctrl";
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@ -124,4 +129,6 @@ Example:
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clock-names = "iface_clk";
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clocks = <&mmcc MDSS_AHB_CLK>;
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vddio-supply = <&pma8084_l12>;
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qcom,dsi-phy-regulator-ldo-mode;
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};
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@ -30,6 +30,7 @@
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enum msm_dsi_phy_type {
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MSM_DSI_PHY_28NM_HPM,
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MSM_DSI_PHY_28NM_LP,
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MSM_DSI_PHY_20NM,
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MSM_DSI_PHY_MAX
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};
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@ -34,6 +34,7 @@
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#define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
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#define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
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#define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
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#define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
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#define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
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#define DSI_6G_REG_SHIFT 4
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@ -117,6 +118,23 @@ static const struct dsi_config dsi_cfgs[] = {
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},
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},
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},
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{ /* 8x94 */
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.major = MSM_DSI_VER_MAJOR_6G,
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.minor = MSM_DSI_6G_VER_MINOR_V1_3,
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.io_offset = DSI_6G_REG_SHIFT,
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.reg_cfg = {
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.num = 7,
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.regs = {
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{"gdsc", -1, -1, -1, -1},
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{"vdda", 1250000, 1250000, 100000, 100},
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{"vddio", 1800000, 1800000, 100000, 100},
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{"vcca", 1000000, 1000000, 10000, 100},
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{"vdd", 1800000, 1800000, 100000, 100},
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{"lab_reg", -1, -1, -1, -1},
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{"ibb_reg", -1, -1, -1, -1},
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},
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}
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},
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};
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static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
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@ -66,6 +66,8 @@ struct msm_dsi_phy {
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struct dsi_dphy_timing timing;
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const struct dsi_phy_cfg *cfg;
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bool regulator_ldo_mode;
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struct msm_dsi_pll *pll;
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};
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@ -406,6 +408,115 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
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return 0;
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}
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static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
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{
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void __iomem *base = phy->reg_base;
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if (!enable) {
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
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return;
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}
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if (phy->regulator_ldo_mode) {
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
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return;
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}
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/* non LDO mode */
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
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}
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static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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const unsigned long bit_rate, const unsigned long esc_rate)
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{
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struct dsi_dphy_timing *timing = &phy->timing;
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int i;
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void __iomem *base = phy->base;
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u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
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DBG("");
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if (dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
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pr_err("%s: D-PHY timing calculation failed\n", __func__);
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return -EINVAL;
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}
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dsi_20nm_phy_regulator_ctrl(phy, true);
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
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dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
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for (i = 0; i < 4; i++) {
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
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(i >> 1) * 0x40);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
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}
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
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DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
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DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
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DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
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if (timing->clk_zero & BIT(8))
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
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DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
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DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
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DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
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DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
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DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
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DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
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DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
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DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
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DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
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dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
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DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
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dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
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dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
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/* make sure everything is written before enable */
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wmb();
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dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
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return 0;
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}
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static int dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
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{
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dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
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dsi_20nm_phy_regulator_ctrl(phy, false);
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return 0;
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}
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static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
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{
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int ret;
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@ -456,6 +567,21 @@ static const struct dsi_phy_cfg dsi_phy_cfgs[MSM_DSI_PHY_MAX] = {
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.disable = dsi_28nm_phy_disable,
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}
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},
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[MSM_DSI_PHY_20NM] = {
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.type = MSM_DSI_PHY_20NM,
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.src_pll_truthtable = { {false, true}, {false, true} },
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.reg_cfg = {
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.num = 2,
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.regs = {
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{"vddio", 1800000, 1800000, 100000, 100},
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{"vcca", 1000000, 1000000, 10000, 100},
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},
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},
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.ops = {
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.enable = dsi_20nm_phy_enable,
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.disable = dsi_20nm_phy_disable,
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}
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},
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};
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static const struct of_device_id dsi_phy_dt_match[] = {
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@ -463,6 +589,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
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.data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_HPM],},
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{ .compatible = "qcom,dsi-phy-28nm-lp",
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.data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_LP],},
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{ .compatible = "qcom,dsi-phy-20nm",
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.data = &dsi_phy_cfgs[MSM_DSI_PHY_20NM],},
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{}
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};
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@ -492,6 +620,9 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
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goto fail;
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}
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phy->regulator_ldo_mode = of_property_read_bool(pdev->dev.of_node,
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"qcom,dsi-phy-regulator-ldo-mode");
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phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
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if (IS_ERR(phy->base)) {
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dev_err(&pdev->dev, "%s: failed to map phy base\n", __func__);
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