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stmmac: intel: Update PCH PTP clock rate from 200MHz to 204.8MHz

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Current Intel platform has an output of ~976ms interval
when probed on 1 Pulse-per-Second(PPS) hardware pin.

The correct PTP clock frequency for PCH GbE should be 204.8MHz
instead of 200MHz. PSE GbE PTP clock rate remains at 200MHz.

Fixes: 58da0cfa6c ("net: stmmac: create dwmac-intel.c to contain all Intel platform")
Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
Signed-off-by: Tan, Tee Min <tee.min.tan@intel.com>
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Gan Yi Fang <yi.fang.gan@intel.com>
Link: https://lore.kernel.org/r/20221108020811.12919-1-yi.fang.gan@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Tan, Tee Min 2022-11-07 21:08:11 -05:00 committed by Jakub Kicinski
parent d75aed1428
commit dcea1a8107
1 changed files with 9 additions and 2 deletions
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11
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
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@ -629,7 +629,6 @@ static int ehl_common_data(struct pci_dev *pdev,
{ {
plat->rx_queues_to_use = 8; plat->rx_queues_to_use = 8;
plat->tx_queues_to_use = 8; plat->tx_queues_to_use = 8;
plat->clk_ptp_rate = 200000000;
plat->use_phy_wol = 1; plat->use_phy_wol = 1;
plat->safety_feat_cfg->tsoee = 1; plat->safety_feat_cfg->tsoee = 1;
@ -654,6 +653,8 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
plat->serdes_powerup = intel_serdes_powerup; plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown; plat->serdes_powerdown = intel_serdes_powerdown;
plat->clk_ptp_rate = 204800000;
return ehl_common_data(pdev, plat); return ehl_common_data(pdev, plat);
} }
@ -667,6 +668,8 @@ static int ehl_rgmii_data(struct pci_dev *pdev,
plat->bus_id = 1; plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_RGMII; plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
plat->clk_ptp_rate = 204800000;
return ehl_common_data(pdev, plat); return ehl_common_data(pdev, plat);
} }
@ -683,6 +686,8 @@ static int ehl_pse0_common_data(struct pci_dev *pdev,
plat->bus_id = 2; plat->bus_id = 2;
plat->addr64 = 32; plat->addr64 = 32;
plat->clk_ptp_rate = 200000000;
intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
return ehl_common_data(pdev, plat); return ehl_common_data(pdev, plat);
@ -722,6 +727,8 @@ static int ehl_pse1_common_data(struct pci_dev *pdev,
plat->bus_id = 3; plat->bus_id = 3;
plat->addr64 = 32; plat->addr64 = 32;
plat->clk_ptp_rate = 200000000;
intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ); intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
return ehl_common_data(pdev, plat); return ehl_common_data(pdev, plat);
@ -757,7 +764,7 @@ static int tgl_common_data(struct pci_dev *pdev,
{ {
plat->rx_queues_to_use = 6; plat->rx_queues_to_use = 6;
plat->tx_queues_to_use = 4; plat->tx_queues_to_use = 4;
plat->clk_ptp_rate = 200000000; plat->clk_ptp_rate = 204800000;
plat->speed_mode_2500 = intel_speed_mode_2500; plat->speed_mode_2500 = intel_speed_mode_2500;
plat->safety_feat_cfg->tsoee = 1; plat->safety_feat_cfg->tsoee = 1;