Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits)
DMAENGINE: at_hdmac: locking fixlet
DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l
dma: dmatest: fix potential sign bug
ioat2: catch and recover from broken vtd configurations v6
DMAENGINE: add runtime slave control to COH 901 318 v3
DMAENGINE: add runtime slave config to DMA40 v3
DMAENGINE: generic slave channel control v3
dmaengine: Driver for Topcliff PCH DMA controller
intel_mid: Add Mrst & Mfld DMA Drivers
drivers/dma: Eliminate a NULL pointer dereference
dma/timb_dma: compile warning on 32 bit
DMAENGINE: ste_dma40: support older silicon
DMAENGINE: ste_dma40: support disabling physical channels
DMAENGINE: ste_dma40: no disabled phy channels on ux500
DMAENGINE: ste_dma40: fix suspend bug
DMAENGINE: ste_dma40: add DB8500 memcpy channels
DMAENGINE: ste_dma40: no flow control on memcpy
DMAENGINE: ste_dma40: arch updates for LCLA and LCPA
DMAENGINE: ste_dma40: allocate LCLA dynamically
DMAENGINE: ste_dma40: no premature stop
...
Fix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c
This commit is contained in:
Linus Torvalds
@@ -114,11 +114,17 @@ enum dma_ctrl_flags {
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* @DMA_TERMINATE_ALL: terminate all ongoing transfers
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* @DMA_PAUSE: pause ongoing transfers
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* @DMA_RESUME: resume paused transfer
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* @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
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* that need to runtime reconfigure the slave channels (as opposed to passing
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* configuration data in statically from the platform). An additional
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* argument of struct dma_slave_config must be passed in with this
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* command.
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*/
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enum dma_ctrl_cmd {
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DMA_TERMINATE_ALL,
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DMA_PAUSE,
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DMA_RESUME,
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DMA_SLAVE_CONFIG,
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};
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/**
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@@ -199,6 +205,71 @@ struct dma_chan_dev {
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atomic_t *idr_ref;
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};
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/**
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* enum dma_slave_buswidth - defines bus with of the DMA slave
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* device, source or target buses
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*/
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enum dma_slave_buswidth {
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DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
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DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
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DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
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DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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};
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/**
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* struct dma_slave_config - dma slave channel runtime config
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* @direction: whether the data shall go in or out on this slave
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* channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
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* legal values, DMA_BIDIRECTIONAL is not acceptable since we
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* need to differentiate source and target addresses.
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* @src_addr: this is the physical address where DMA slave data
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* should be read (RX), if the source is memory this argument is
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* ignored.
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* @dst_addr: this is the physical address where DMA slave data
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* should be written (TX), if the source is memory this argument
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* is ignored.
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* @src_addr_width: this is the width in bytes of the source (RX)
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* register where DMA data shall be read. If the source
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* is memory this may be ignored depending on architecture.
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* Legal values: 1, 2, 4, 8.
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* @dst_addr_width: same as src_addr_width but for destination
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* target (TX) mutatis mutandis.
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* @src_maxburst: the maximum number of words (note: words, as in
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* units of the src_addr_width member, not bytes) that can be sent
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* in one burst to the device. Typically something like half the
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* FIFO depth on I/O peripherals so you don't overflow it. This
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* may or may not be applicable on memory sources.
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* @dst_maxburst: same as src_maxburst but for destination target
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* mutatis mutandis.
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*
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* This struct is passed in as configuration data to a DMA engine
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* in order to set up a certain channel for DMA transport at runtime.
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* The DMA device/engine has to provide support for an additional
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* command in the channel config interface, DMA_SLAVE_CONFIG
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* and this struct will then be passed in as an argument to the
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* DMA engine device_control() function.
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*
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* The rationale for adding configuration information to this struct
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* is as follows: if it is likely that most DMA slave controllers in
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* the world will support the configuration option, then make it
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* generic. If not: if it is fixed so that it be sent in static from
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* the platform data, then prefer to do that. Else, if it is neither
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* fixed at runtime, nor generic enough (such as bus mastership on
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* some CPU family and whatnot) then create a custom slave config
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* struct and pass that, then make this config a member of that
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* struct, if applicable.
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*/
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struct dma_slave_config {
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enum dma_data_direction direction;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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enum dma_slave_buswidth src_addr_width;
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enum dma_slave_buswidth dst_addr_width;
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u32 src_maxburst;
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u32 dst_maxburst;
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};
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static inline const char *dma_chan_name(struct dma_chan *chan)
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{
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return dev_name(&chan->dev->device);
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86
include/linux/intel_mid_dma.h
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86
include/linux/intel_mid_dma.h
Normal file
@@ -0,0 +1,86 @@
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/*
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* intel_mid_dma.h - Intel MID DMA Drivers
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*
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* Copyright (C) 2008-10 Intel Corp
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* Author: Vinod Koul <vinod.koul@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*
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*/
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#ifndef __INTEL_MID_DMA_H__
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#define __INTEL_MID_DMA_H__
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#include <linux/dmaengine.h>
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/*DMA transaction width, src and dstn width would be same
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The DMA length must be width aligned,
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for 32 bit width the length must be 32 bit (4bytes) aligned only*/
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enum intel_mid_dma_width {
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LNW_DMA_WIDTH_8BIT = 0x0,
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LNW_DMA_WIDTH_16BIT = 0x1,
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LNW_DMA_WIDTH_32BIT = 0x2,
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};
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/*DMA mode configurations*/
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enum intel_mid_dma_mode {
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LNW_DMA_PER_TO_MEM = 0, /*periphral to memory configuration*/
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LNW_DMA_MEM_TO_PER, /*memory to periphral configuration*/
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LNW_DMA_MEM_TO_MEM, /*mem to mem confg (testing only)*/
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};
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/*DMA handshaking*/
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enum intel_mid_dma_hs_mode {
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LNW_DMA_HW_HS = 0, /*HW Handshaking only*/
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LNW_DMA_SW_HS = 1, /*SW Handshaking not recommended*/
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};
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/*Burst size configuration*/
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enum intel_mid_dma_msize {
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LNW_DMA_MSIZE_1 = 0x0,
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LNW_DMA_MSIZE_4 = 0x1,
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LNW_DMA_MSIZE_8 = 0x2,
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LNW_DMA_MSIZE_16 = 0x3,
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LNW_DMA_MSIZE_32 = 0x4,
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LNW_DMA_MSIZE_64 = 0x5,
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};
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/**
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* struct intel_mid_dma_slave - DMA slave structure
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*
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* @dirn: DMA trf direction
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* @src_width: tx register width
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* @dst_width: rx register width
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* @hs_mode: HW/SW handshaking mode
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* @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem)
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* @src_msize: Source DMA burst size
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* @dst_msize: Dst DMA burst size
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* @device_instance: DMA peripheral device instance, we can have multiple
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* peripheral device connected to single DMAC
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*/
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struct intel_mid_dma_slave {
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enum dma_data_direction dirn;
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enum intel_mid_dma_width src_width; /*width of DMA src txn*/
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enum intel_mid_dma_width dst_width; /*width of DMA dst txn*/
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enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/
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enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
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enum intel_mid_dma_msize src_msize; /*size if src burst*/
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enum intel_mid_dma_msize dst_msize; /*size of dst burst*/
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unsigned int device_instance; /*0, 1 for periphral instance*/
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};
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#endif /*__INTEL_MID_DMA_H__*/
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37
include/linux/pch_dma.h
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37
include/linux/pch_dma.h
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@@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef PCH_DMA_H
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#define PCH_DMA_H
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#include <linux/dmaengine.h>
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enum pch_dma_width {
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PCH_DMA_WIDTH_1_BYTE,
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PCH_DMA_WIDTH_2_BYTES,
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PCH_DMA_WIDTH_4_BYTES,
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};
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struct pch_dma_slave {
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struct device *dma_dev;
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unsigned int chan_id;
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dma_addr_t tx_reg;
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dma_addr_t rx_reg;
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enum pch_dma_width width;
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};
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#endif
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