forked from Minki/linux
dmaengine: tegra-apb: Clean up suspend-resume
It is enough to check whether hardware is busy on suspend and to reset
it across of suspend-resume because:
1. Channel's configuration is fully re-programmed on each DMA
transfer anyways.
2. Context save-restore of an active channel won't end up well without
pausing transfer prior to the context's saving, but note that every
channel shall be idling at the time of suspend, so save-restore is
not needed at all.
3. The only case where context save-restore may be useful is when
channel is in a paused state during suspend. But channel's pausing
could be supported only on Tegra114+ and this functionality wasn't
implemented by the driver for years now because there is no need for
it in upstream kernel.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20200209163356.6439-14-digetx@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Osipenko
Vinod Koul
parent
84a3f375ee
commit
dcb394b6b5
@ -221,9 +221,6 @@ struct tegra_dma {
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*/
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u32 global_pause_count;
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/* Some register need to be cache before suspend */
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u32 reg_gen;
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/* Last member of the structure */
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struct tegra_dma_channel channels[0];
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};
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@ -1390,6 +1387,36 @@ static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
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.support_separate_wcount_reg = true,
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};
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static int tegra_dma_init_hw(struct tegra_dma *tdma)
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{
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int err;
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err = reset_control_assert(tdma->rst);
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if (err) {
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dev_err(tdma->dev, "failed to assert reset: %d\n", err);
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return err;
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}
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err = clk_enable(tdma->dma_clk);
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if (err) {
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dev_err(tdma->dev, "failed to enable clk: %d\n", err);
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return err;
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}
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/* reset DMA controller */
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udelay(2);
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reset_control_deassert(tdma->rst);
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/* enable global DMA registers */
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tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFF);
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clk_disable(tdma->dma_clk);
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return 0;
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}
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static int tegra_dma_probe(struct platform_device *pdev)
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{
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const struct tegra_dma_chip_data *cdata;
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@ -1431,25 +1458,13 @@ static int tegra_dma_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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ret = tegra_dma_init_hw(tdma);
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if (ret)
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goto err_clk_unprepare;
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pm_runtime_irq_safe(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ret = pm_runtime_get_sync(&pdev->dev);
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if (ret < 0)
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goto err_pm_disable;
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/* Reset DMA controller */
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reset_control_assert(tdma->rst);
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udelay(2);
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reset_control_deassert(tdma->rst);
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/* Enable global DMA registers */
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tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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pm_runtime_put(&pdev->dev);
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INIT_LIST_HEAD(&tdma->dma_dev.channels);
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for (i = 0; i < cdata->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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@ -1547,6 +1562,8 @@ err_unregister_dma_dev:
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err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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err_clk_unprepare:
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clk_unprepare(tdma->dma_clk);
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return ret;
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@ -1566,26 +1583,6 @@ static int tegra_dma_remove(struct platform_device *pdev)
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static int tegra_dma_runtime_suspend(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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unsigned int i;
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tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
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for (i = 0; i < tdma->chip_data->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
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/* Only save the state of DMA channels that are in use */
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if (!tdc->config_init)
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continue;
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ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
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ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
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ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
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ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
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ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
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if (tdma->chip_data->support_separate_wcount_reg)
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ch_reg->wcount = tdc_read(tdc,
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TEGRA_APBDMA_CHAN_WCOUNT);
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}
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clk_disable(tdma->dma_clk);
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@ -1595,46 +1592,51 @@ static int tegra_dma_runtime_suspend(struct device *dev)
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static int tegra_dma_runtime_resume(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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return clk_enable(tdma->dma_clk);
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}
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static int __maybe_unused tegra_dma_dev_suspend(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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unsigned long flags;
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unsigned int i;
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int ret;
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ret = clk_enable(tdma->dma_clk);
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if (ret < 0) {
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dev_err(dev, "clk_enable failed: %d\n", ret);
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return ret;
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}
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tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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bool busy;
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for (i = 0; i < tdma->chip_data->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
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/* Only restore the state of DMA channels that are in use */
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if (!tdc->config_init)
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continue;
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tasklet_kill(&tdc->tasklet);
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if (tdma->chip_data->support_separate_wcount_reg)
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tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
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ch_reg->wcount);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
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tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
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ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB);
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spin_lock_irqsave(&tdc->lock, flags);
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busy = tdc->busy;
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spin_unlock_irqrestore(&tdc->lock, flags);
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if (busy) {
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dev_err(tdma->dev, "channel %u busy\n", i);
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return -EBUSY;
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}
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}
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return 0;
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return pm_runtime_force_suspend(dev);
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}
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static int __maybe_unused tegra_dma_dev_resume(struct device *dev)
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{
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struct tegra_dma *tdma = dev_get_drvdata(dev);
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int err;
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err = tegra_dma_init_hw(tdma);
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if (err)
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return err;
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return pm_runtime_force_resume(dev);
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}
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static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
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NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_dev_suspend, tegra_dma_dev_resume)
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};
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static const struct of_device_id tegra_dma_of_match[] = {
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