staging: brcm80211: removed ASSERTs from aiutils.c
Code cleanup. Cc: devel@linuxdriverproject.org Cc: linux-wireless@vger.kernel.org Cc: Brett Rudley <brudley@broadcom.com> Cc: Henry Ptasinski <henryp@broadcom.com> Cc: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
6fa05a5e0c
commit
dc98693b2a
@ -601,7 +601,6 @@ static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
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uint pciidx, pcieidx, pcirev, pcierev;
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cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
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ASSERT(cc);
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/* get chipcommon rev */
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sii->pub.ccrev = (int)ai_corerev(&sii->pub);
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@ -747,7 +746,6 @@ static __used void ai_nvram_process(si_info_t *sii, char *pvars)
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if (sii->pub.boardtype == 0) {
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SI_ERROR(("si_doattach: unknown board type\n"));
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ASSERT(sii->pub.boardtype);
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}
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sii->pub.boardflags = getintvar(pvars, "boardflags");
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@ -764,8 +762,6 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid,
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uint socitype;
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uint origidx;
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ASSERT(GOODREGS(regs));
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memset((unsigned char *) sii, 0, sizeof(si_info_t));
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savewin = 0;
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@ -902,7 +898,6 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid,
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ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
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if (PCIE(sii)) {
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ASSERT(sii->pch != NULL);
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pcicore_attach(sii->pch, pvars, SI_DOATTACH);
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}
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@ -1094,8 +1089,6 @@ void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
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INTR_OFF(sii, *intr_val);
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*origidx = sii->curidx;
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cc = ai_setcore(sih, coreid, 0);
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ASSERT(cc != NULL);
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return cc;
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}
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@ -1142,10 +1135,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
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sii = SI_INFO(sih);
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ASSERT(GOODIDX(coreidx));
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ASSERT(regoff < SI_CORE_SIZE);
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ASSERT((val & ~mask) == 0);
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if (coreidx >= SI_MAXCORES)
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return 0;
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@ -1156,7 +1145,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
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if (!sii->regs[coreidx]) {
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sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
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SI_CORE_SIZE);
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ASSERT(GOODREGS(sii->regs[coreidx]));
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}
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r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
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} else if (sih->bustype == PCI_BUS) {
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@ -1199,7 +1187,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
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r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx)
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+ regoff);
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}
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ASSERT(r != NULL);
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/* mask and set */
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if (mask || val) {
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@ -1229,7 +1216,6 @@ void ai_core_disable(si_t *sih, u32 bits)
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sii = SI_INFO(sih);
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ASSERT(GOODREGS(sii->curwrap));
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ai = sii->curwrap;
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/* if core is already in reset, just return */
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@ -1256,7 +1242,6 @@ void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
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u32 dummy;
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sii = SI_INFO(sih);
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ASSERT(GOODREGS(sii->curwrap));
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ai = sii->curwrap;
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/*
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@ -1284,8 +1269,6 @@ static uint ai_slowclk_src(si_info_t *sii)
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chipcregs_t *cc;
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u32 val;
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ASSERT(SI_FAST(sii) || ai_coreid(&sii->pub) == CC_CORE_ID);
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if (sii->pub.ccrev < 6) {
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if (sii->pub.bustype == PCI_BUS) {
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pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
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@ -1301,20 +1284,15 @@ static uint ai_slowclk_src(si_info_t *sii)
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return SCC_SS_XTAL;
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}
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/* return the ILP (slowclock) min or max frequency */
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/*
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* return the ILP (slowclock) min or max frequency
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* precondition: we've established the chip has dynamic clk control
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*/
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static uint ai_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
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{
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u32 slowclk;
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uint div;
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ASSERT(SI_FAST(sii) || ai_coreid(&sii->pub) == CC_CORE_ID);
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/*
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* shouldn't be here unless we've established
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* the chip has dynamic clk control
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*/
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ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL);
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slowclk = ai_slowclk_src(sii);
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if (sii->pub.ccrev < 6) {
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if (slowclk == SCC_SS_PCI)
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@ -1335,8 +1313,6 @@ static uint ai_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
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else if (slowclk == SCC_SS_PCI)
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return max_freq ? (PCIMAXFREQ / div)
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: (PCIMINFREQ / div);
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else
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ASSERT(0);
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} else {
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/* Chipc rev 10 is InstaClock */
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div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
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@ -1398,7 +1374,6 @@ void ai_clkctl_init(si_t *sih)
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if (cc == NULL)
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return;
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}
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ASSERT(cc != NULL);
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/* set all Instaclk chip ILP to 1 MHz */
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if (sih->ccrev >= 10)
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@ -1449,7 +1424,6 @@ u16 ai_clkctl_fast_pwrup_delay(si_t *sih)
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if (cc == NULL)
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goto done;
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}
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ASSERT(cc != NULL);
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slowminfreq = ai_slowclk_freq(sii, false, cc);
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fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
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@ -1570,12 +1544,6 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
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if (sii->pub.ccrev < 6)
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return false;
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/*
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* Chips with ccrev 10 are EOL and they
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* don't have SYCC_HR which we use below
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*/
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ASSERT(sii->pub.ccrev != 10);
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if (!fast) {
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INTR_OFF(sii, intr_val);
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origidx = sii->curidx;
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@ -1591,7 +1559,6 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
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if (cc == NULL)
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goto done;
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}
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ASSERT(cc != NULL);
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if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
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goto done;
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@ -1617,7 +1584,6 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
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u32 htavail = CCS_HTAVAIL;
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SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
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== 0), PMU_MAX_TRANSITION_DLY);
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ASSERT(R_REG(&cc->clk_ctl_st) & htavail);
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} else {
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udelay(PLL_DELAY);
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}
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@ -1646,7 +1612,7 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
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break;
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default:
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ASSERT(0);
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break;
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}
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done:
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@ -1662,9 +1628,6 @@ int ai_devpath(si_t *sih, char *path, int size)
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{
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int slen;
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ASSERT(path != NULL);
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ASSERT(size >= SI_DEVPATH_BUFSZ);
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if (!path || size <= 0)
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return -1;
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@ -1674,7 +1637,6 @@ int ai_devpath(si_t *sih, char *path, int size)
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slen = snprintf(path, (size_t) size, "sb/%u/", ai_coreidx(sih));
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break;
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case PCI_BUS:
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ASSERT((SI_INFO(sih))->pbus != NULL);
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slen = snprintf(path, (size_t) size, "pci/%u/%u/",
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((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
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PCI_SLOT(
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@ -1683,7 +1645,6 @@ int ai_devpath(si_t *sih, char *path, int size)
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default:
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slen = -1;
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ASSERT(0);
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break;
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}
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@ -1836,9 +1797,6 @@ void ai_pci_setup(si_t *sih, uint coremask)
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if (sii->pub.bustype != PCI_BUS)
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return;
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ASSERT(PCI(sii) || PCIE(sii));
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ASSERT(sii->pub.buscoreidx != BADIDX);
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if (PCI(sii)) {
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/* get current core index */
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idx = sii->curidx;
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@ -1895,8 +1853,6 @@ int ai_pci_fixcfg(si_t *sih)
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si_info_t *sii = SI_INFO(sih);
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ASSERT(sii->pub.bustype == PCI_BUS);
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/* Fixup PI in SROM shadow area to enable the correct PCI core access */
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/* save the current index */
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origidx = ai_coreidx(&sii->pub);
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@ -1905,12 +1861,10 @@ int ai_pci_fixcfg(si_t *sih)
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if (sii->pub.buscoretype == PCIE_CORE_ID) {
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pcieregs = ai_setcore(&sii->pub, PCIE_CORE_ID, 0);
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regs = pcieregs;
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ASSERT(pcieregs != NULL);
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reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
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} else if (sii->pub.buscoretype == PCI_CORE_ID) {
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pciregs = ai_setcore(&sii->pub, PCI_CORE_ID, 0);
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regs = pciregs;
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ASSERT(pciregs != NULL);
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reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
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}
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pciidx = ai_coreidx(&sii->pub);
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@ -2012,7 +1966,6 @@ bool ai_deviceremoved(si_t *sih)
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switch (sih->bustype) {
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case PCI_BUS:
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ASSERT(sii->pbus != NULL);
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pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
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if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
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return true;
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