forked from Minki/linux
ARM: dts: sti: move some nodes out of the soc section in stih407-family.dtsi
Move all nodes without reg property out of the soc section of stih407-family.dtsi and DT including stih407-family.dtsi. This avoid to set a <0> reg property. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Alain Volmat
Patrice Chotard
parent
c0749d2d1f
commit
dc3477ca69
@ -115,6 +115,134 @@
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status = "okay";
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};
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restart: restart-controller {
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compatible = "st,stih407-restart";
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller {
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compatible = "st,stih407-powerdown";
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#reset-cells = <1>;
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};
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softreset: softreset-controller {
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compatible = "st,stih407-softreset";
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#reset-cells = <1>;
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};
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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irq-syscfg {
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compatible = "st,stih407-irq-syscfg";
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st,syscfg = <&syscfg_core>;
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st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
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<ST_IRQ_SYSCFG_PMU_1>;
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st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
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<ST_IRQ_SYSCFG_DISABLED>;
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};
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usb2_picophy0: phy1 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY2_RESET>;
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reset-names = "global", "port";
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};
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miphy28lp_phy: miphy28lp {
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compatible = "st,miphy28lp-phy";
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st,syscfg = <&syscfg_core>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@9b22000 {
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reg = <0x9b22000 0xff>,
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<0x9b09000 0xff>,
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<0x9b04000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x114 0x818 0xe0 0xec>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
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};
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phy_port1: port@9b2a000 {
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reg = <0x9b2a000 0xff>,
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<0x9b19000 0xff>,
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<0x9b14000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x118 0x81c 0xe4 0xf0>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
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};
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phy_port2: port@8f95000 {
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reg = <0x8f95000 0xff>,
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<0x8f90000 0xff>;
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reg-names = "pipew",
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"usb3-up";
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st,syscfg = <0x11c 0x820>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
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};
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};
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st231_gp0: st231-gp0 {
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compatible = "st,st231-rproc";
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memory-region = <&gp0_reserved>;
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resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x22c>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
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};
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st231_delta: st231-delta {
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compatible = "st,st231-rproc";
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memory-region = <&delta_reserved>;
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resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x224>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
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};
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delta0 {
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compatible = "st,st-delta";
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clock-names = "delta",
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"delta-st231",
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"delta-flash-promip";
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clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
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<&clk_s_c0_flexgen CLK_ST231_DMU>,
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<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -122,31 +250,6 @@
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ranges;
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compatible = "simple-bus";
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restart: restart-controller@0 {
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compatible = "st,stih407-restart";
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reg = <0 0>;
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller@0 {
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compatible = "st,stih407-powerdown";
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reg = <0 0>;
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#reset-cells = <1>;
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};
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softreset: softreset-controller@0 {
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compatible = "st,stih407-softreset";
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reg = <0 0>;
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#reset-cells = <1>;
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};
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picophyreset: picophyreset-controller@0 {
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compatible = "st,stih407-picophyreset";
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reg = <0 0>;
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#reset-cells = <1>;
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};
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syscfg_sbc: sbc-syscfg@9620000 {
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compatible = "st,stih407-sbc-syscfg", "syscon";
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reg = <0x9620000 0x1000>;
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@ -189,16 +292,6 @@
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reg = <0x94b5100 0x1000>;
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};
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irq-syscfg@0 {
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compatible = "st,stih407-irq-syscfg";
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reg = <0 0>;
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st,syscfg = <&syscfg_core>;
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st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
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<ST_IRQ_SYSCFG_PMU_1>;
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st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
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<ST_IRQ_SYSCFG_DISABLED>;
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};
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/* Display */
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vtg_main: sti-vtg-main@8d02800 {
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compatible = "st,vtg";
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@ -389,70 +482,6 @@
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status = "disabled";
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};
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usb2_picophy0: phy1@0 {
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compatible = "st,stih407-usb2-phy";
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reg = <0 0>;
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY2_RESET>;
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reset-names = "global", "port";
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};
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miphy28lp_phy: miphy28lp@0 {
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compatible = "st,miphy28lp-phy";
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st,syscfg = <&syscfg_core>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0 0>;
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phy_port0: port@9b22000 {
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reg = <0x9b22000 0xff>,
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<0x9b09000 0xff>,
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<0x9b04000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x114 0x818 0xe0 0xec>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
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};
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phy_port1: port@9b2a000 {
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reg = <0x9b2a000 0xff>,
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<0x9b19000 0xff>,
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<0x9b14000 0xff>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew";
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st,syscfg = <0x118 0x81c 0xe4 0xf0>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
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};
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phy_port2: port@8f95000 {
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reg = <0x8f95000 0xff>,
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<0x8f90000 0xff>;
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reg-names = "pipew",
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"usb3-up";
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st,syscfg = <0x11c 0x820>;
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
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};
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};
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spi@9840000 {
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compatible = "st,comms-ssc4-spi";
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reg = <0x9840000 0x110>;
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@ -815,34 +844,6 @@
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status = "okay";
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};
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st231_gp0: st231-gp0@0 {
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compatible = "st,st231-rproc";
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reg = <0 0>;
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memory-region = <&gp0_reserved>;
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resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x22c>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
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};
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st231_delta: st231-delta@0 {
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compatible = "st,st231-rproc";
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reg = <0 0>;
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memory-region = <&delta_reserved>;
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resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
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reset-names = "sw_reset";
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clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
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clock-frequency = <600000000>;
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st,syscfg = <&syscfg_core 0x224>;
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#mbox-cells = <1>;
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mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
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mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
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};
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/* fdma audio */
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fdma0: dma-controller@8e20000 {
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compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
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@ -986,16 +987,5 @@
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status = "disabled";
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};
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delta0@0 {
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compatible = "st,st-delta";
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reg = <0 0>;
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clock-names = "delta",
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"delta-st231",
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"delta-flash-promip";
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clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
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<&clk_s_c0_flexgen CLK_ST231_DMU>,
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<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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};
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};
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};
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@ -75,6 +75,13 @@
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};
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};
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miphy28lp_phy: miphy28lp {
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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soc {
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/* Low speed expansion connector */
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uart0: serial@9830000 {
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@ -196,13 +203,6 @@
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status = "okay";
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};
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miphy28lp_phy: miphy28lp@0 {
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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sata1: sata@9b28000 {
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status = "okay";
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};
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@ -37,6 +37,17 @@
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};
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};
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miphy28lp_phy: miphy28lp {
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phy_port0: port@9b22000 {
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st,osc-rdy;
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};
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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soc {
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sbc_serial0: serial@9530000 {
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status = "okay";
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@ -84,17 +95,6 @@
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non-removable;
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};
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miphy28lp_phy: miphy28lp@0 {
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phy_port0: port@9b22000 {
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st,osc-rdy;
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};
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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st_dwc3: dwc3@8f94000 {
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status = "okay";
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};
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@ -71,6 +71,17 @@
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};
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};
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miphy28lp_phy: miphy28lp {
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phy_port0: port@9b22000 {
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st,osc-rdy;
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};
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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soc {
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sbc_serial0: serial@9530000 {
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status = "okay";
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@ -128,17 +139,6 @@
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st,i2c-min-sda-pulse-width-us = <5>;
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};
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miphy28lp_phy: miphy28lp@0 {
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phy_port0: port@9b22000 {
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st,osc-rdy;
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};
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phy_port1: port@9b2a000 {
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st,osc-force-ext;
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};
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};
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st_dwc3: dwc3@8f94000 {
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status = "okay";
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};
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