net: iosm: mmio scratchpad
1) Initializes the Scratchpad region for Host-Device communication. 2) Exposes device capabilities like chip info and device execution stages. Signed-off-by: M Chetan Kumar <m.chetan.kumar@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
M Chetan Kumar
David S. Miller
parent
7f41ce085d
commit
dc0514f5d8
223
drivers/net/wwan/iosm/iosm_ipc_mmio.c
Normal file
223
drivers/net/wwan/iosm/iosm_ipc_mmio.c
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@ -0,0 +1,223 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020-21 Intel Corporation.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/slab.h>
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#include "iosm_ipc_mmio.h"
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/* Definition of MMIO offsets
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* note that MMIO_CI offsets are relative to end of chip info structure
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*/
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/* MMIO chip info size in bytes */
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#define MMIO_CHIP_INFO_SIZE 60
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/* CP execution stage */
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#define MMIO_OFFSET_EXECUTION_STAGE 0x00
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/* Boot ROM Chip Info struct */
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#define MMIO_OFFSET_CHIP_INFO 0x04
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#define MMIO_OFFSET_ROM_EXIT_CODE 0x40
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#define MMIO_OFFSET_PSI_ADDRESS 0x54
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#define MMIO_OFFSET_PSI_SIZE 0x5C
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#define MMIO_OFFSET_IPC_STATUS 0x60
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#define MMIO_OFFSET_CONTEXT_INFO 0x64
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#define MMIO_OFFSET_BASE_ADDR 0x6C
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#define MMIO_OFFSET_END_ADDR 0x74
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#define MMIO_OFFSET_CP_VERSION 0xF0
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#define MMIO_OFFSET_CP_CAPABILITIES 0xF4
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/* Timeout in 50 msec to wait for the modem boot code to write a valid
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* execution stage into mmio area
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*/
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#define IPC_MMIO_EXEC_STAGE_TIMEOUT 50
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/* check if exec stage has one of the valid values */
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static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage)
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{
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switch (stage) {
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case IPC_MEM_EXEC_STAGE_BOOT:
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case IPC_MEM_EXEC_STAGE_PSI:
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case IPC_MEM_EXEC_STAGE_EBL:
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case IPC_MEM_EXEC_STAGE_RUN:
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case IPC_MEM_EXEC_STAGE_CRASH:
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case IPC_MEM_EXEC_STAGE_CD_READY:
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return true;
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default:
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return false;
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}
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}
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void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio)
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{
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u32 cp_cap;
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unsigned int ver;
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ver = ipc_mmio_get_cp_version(ipc_mmio);
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cp_cap = readl(ipc_mmio->base + ipc_mmio->offset.cp_capability);
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ipc_mmio->has_mux_lite = (ver >= IOSM_CP_VERSION) &&
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!(cp_cap & DL_AGGR) && !(cp_cap & UL_AGGR);
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ipc_mmio->has_ul_flow_credit =
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(ver >= IOSM_CP_VERSION) && (cp_cap & UL_FLOW_CREDIT);
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}
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struct iosm_mmio *ipc_mmio_init(void __iomem *mmio, struct device *dev)
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{
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struct iosm_mmio *ipc_mmio = kzalloc(sizeof(*ipc_mmio), GFP_KERNEL);
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int retries = IPC_MMIO_EXEC_STAGE_TIMEOUT;
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enum ipc_mem_exec_stage stage;
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if (!ipc_mmio)
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return NULL;
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ipc_mmio->dev = dev;
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ipc_mmio->base = mmio;
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ipc_mmio->offset.exec_stage = MMIO_OFFSET_EXECUTION_STAGE;
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/* Check for a valid execution stage to make sure that the boot code
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* has correctly initialized the MMIO area.
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*/
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do {
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stage = ipc_mmio_get_exec_stage(ipc_mmio);
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if (ipc_mmio_is_valid_exec_stage(stage))
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break;
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msleep(20);
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} while (retries-- > 0);
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if (!retries) {
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dev_err(ipc_mmio->dev, "invalid exec stage %X", stage);
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goto init_fail;
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}
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ipc_mmio->offset.chip_info = MMIO_OFFSET_CHIP_INFO;
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/* read chip info size and version from chip info structure */
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ipc_mmio->chip_info_version =
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ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info);
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/* Increment of 2 is needed as the size value in the chip info
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* excludes the version and size field, which are always present
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*/
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ipc_mmio->chip_info_size =
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ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info + 1) + 2;
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if (ipc_mmio->chip_info_size != MMIO_CHIP_INFO_SIZE) {
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dev_err(ipc_mmio->dev, "Unexpected Chip Info");
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goto init_fail;
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}
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ipc_mmio->offset.rom_exit_code = MMIO_OFFSET_ROM_EXIT_CODE;
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ipc_mmio->offset.psi_address = MMIO_OFFSET_PSI_ADDRESS;
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ipc_mmio->offset.psi_size = MMIO_OFFSET_PSI_SIZE;
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ipc_mmio->offset.ipc_status = MMIO_OFFSET_IPC_STATUS;
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ipc_mmio->offset.context_info = MMIO_OFFSET_CONTEXT_INFO;
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ipc_mmio->offset.ap_win_base = MMIO_OFFSET_BASE_ADDR;
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ipc_mmio->offset.ap_win_end = MMIO_OFFSET_END_ADDR;
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ipc_mmio->offset.cp_version = MMIO_OFFSET_CP_VERSION;
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ipc_mmio->offset.cp_capability = MMIO_OFFSET_CP_CAPABILITIES;
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return ipc_mmio;
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init_fail:
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kfree(ipc_mmio);
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return NULL;
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}
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enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio)
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{
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if (!ipc_mmio)
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return IPC_MEM_EXEC_STAGE_INVALID;
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return (enum ipc_mem_exec_stage)readl(ipc_mmio->base +
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ipc_mmio->offset.exec_stage);
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}
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void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,
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size_t size)
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{
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if (ipc_mmio && dest)
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memcpy_fromio(dest, ipc_mmio->base + ipc_mmio->offset.chip_info,
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size);
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}
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enum ipc_mem_device_ipc_state ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio)
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{
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if (!ipc_mmio)
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return IPC_MEM_DEVICE_IPC_INVALID;
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return (enum ipc_mem_device_ipc_state)
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readl(ipc_mmio->base + ipc_mmio->offset.ipc_status);
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}
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enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio)
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{
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if (!ipc_mmio)
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return IMEM_ROM_EXIT_FAIL;
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return (enum rom_exit_code)readl(ipc_mmio->base +
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ipc_mmio->offset.rom_exit_code);
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}
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void ipc_mmio_config(struct iosm_mmio *ipc_mmio)
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{
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if (!ipc_mmio)
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return;
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/* AP memory window (full window is open and active so that modem checks
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* each AP address) 0 means don't check on modem side.
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*/
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iowrite64_lo_hi(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base);
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iowrite64_lo_hi(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end);
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iowrite64_lo_hi(ipc_mmio->context_info_addr,
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ipc_mmio->base + ipc_mmio->offset.context_info);
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}
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void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,
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u32 size)
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{
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if (!ipc_mmio)
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return;
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iowrite64_lo_hi(addr, ipc_mmio->base + ipc_mmio->offset.psi_address);
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writel(size, ipc_mmio->base + ipc_mmio->offset.psi_size);
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}
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void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, phys_addr_t addr)
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{
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if (!ipc_mmio)
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return;
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/* store context_info address. This will be stored in the mmio area
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* during IPC_MEM_DEVICE_IPC_INIT state via ipc_mmio_config()
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*/
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ipc_mmio->context_info_addr = addr;
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}
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int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio)
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{
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return ipc_mmio ? readl(ipc_mmio->base + ipc_mmio->offset.cp_version) :
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-EFAULT;
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}
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193
drivers/net/wwan/iosm/iosm_ipc_mmio.h
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193
drivers/net/wwan/iosm/iosm_ipc_mmio.h
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@ -0,0 +1,193 @@
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (C) 2020-21 Intel Corporation.
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*/
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#ifndef IOSM_IPC_MMIO_H
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#define IOSM_IPC_MMIO_H
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/* Minimal IOSM CP VERSION which has valid CP_CAPABILITIES field */
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#define IOSM_CP_VERSION 0x0100UL
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/* DL dir Aggregation support mask */
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#define DL_AGGR BIT(23)
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/* UL dir Aggregation support mask */
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#define UL_AGGR BIT(22)
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/* UL flow credit support mask */
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#define UL_FLOW_CREDIT BIT(21)
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/* Possible states of the IPC finite state machine. */
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enum ipc_mem_device_ipc_state {
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IPC_MEM_DEVICE_IPC_UNINIT,
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IPC_MEM_DEVICE_IPC_INIT,
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IPC_MEM_DEVICE_IPC_RUNNING,
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IPC_MEM_DEVICE_IPC_RECOVERY,
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IPC_MEM_DEVICE_IPC_ERROR,
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IPC_MEM_DEVICE_IPC_DONT_CARE,
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IPC_MEM_DEVICE_IPC_INVALID = -1
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};
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/* Boot ROM exit status. */
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enum rom_exit_code {
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IMEM_ROM_EXIT_OPEN_EXT = 0x01,
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IMEM_ROM_EXIT_OPEN_MEM = 0x02,
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IMEM_ROM_EXIT_CERT_EXT = 0x10,
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IMEM_ROM_EXIT_CERT_MEM = 0x20,
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IMEM_ROM_EXIT_FAIL = 0xFF
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};
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/* Boot stages */
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enum ipc_mem_exec_stage {
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IPC_MEM_EXEC_STAGE_RUN = 0x600DF00D,
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IPC_MEM_EXEC_STAGE_CRASH = 0x8BADF00D,
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IPC_MEM_EXEC_STAGE_CD_READY = 0xBADC0DED,
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IPC_MEM_EXEC_STAGE_BOOT = 0xFEEDB007,
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IPC_MEM_EXEC_STAGE_PSI = 0xFEEDBEEF,
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IPC_MEM_EXEC_STAGE_EBL = 0xFEEDCAFE,
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IPC_MEM_EXEC_STAGE_INVALID = 0xFFFFFFFF
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};
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/* mmio scratchpad info */
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struct mmio_offset {
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int exec_stage;
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int chip_info;
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int rom_exit_code;
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int psi_address;
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int psi_size;
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int ipc_status;
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int context_info;
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int ap_win_base;
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int ap_win_end;
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int cp_version;
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int cp_capability;
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};
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/**
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* struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
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* @base: Base address of MMIO region
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* @dev: Pointer to device structure
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* @offset: Start offset
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* @context_info_addr: Physical base address of context info structure
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* @chip_info_version: Version of chip info structure
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* @chip_info_size: Size of chip info structure
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* @has_mux_lite: It doesn't support mux aggergation
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* @has_ul_flow_credit: Ul flow credit support
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* @has_slp_no_prot: Device sleep no protocol support
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* @has_mcr_support: Usage of mcr support
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*/
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struct iosm_mmio {
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unsigned char __iomem *base;
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struct device *dev;
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struct mmio_offset offset;
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phys_addr_t context_info_addr;
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unsigned int chip_info_version;
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unsigned int chip_info_size;
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u8 has_mux_lite:1,
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has_ul_flow_credit:1,
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has_slp_no_prot:1,
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has_mcr_support:1;
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};
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/**
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* ipc_mmio_init - Allocate mmio instance data
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* @mmio_addr: Mapped AP base address of the MMIO area.
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* @dev: Pointer to device structure
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*
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* Returns: address of mmio instance data or NULL if fails.
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*/
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struct iosm_mmio *ipc_mmio_init(void __iomem *mmio_addr, struct device *dev);
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/**
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* ipc_mmio_set_psi_addr_and_size - Set start address and size of the
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* primary system image (PSI) for the
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* FW dowload.
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* @ipc_mmio: Pointer to mmio instance
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* @addr: PSI address
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* @size: PSI immage size
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*/
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void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,
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u32 size);
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/**
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* ipc_mmio_set_contex_info_addr - Stores the Context Info Address in
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* MMIO instance to share it with CP during
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* mmio_init.
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* @ipc_mmio: Pointer to mmio instance
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* @addr: 64-bit address of AP context information.
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*/
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void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio,
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phys_addr_t addr);
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/**
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* ipc_mmio_get_cp_version - Write context info and AP memory range addresses.
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* This needs to be called when CP is in
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* IPC_MEM_DEVICE_IPC_INIT state
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: cp version else failure value on error
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*/
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int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_cp_version - Get the CP IPC version
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: version number on success and failure value on error.
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*/
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int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_rom_exit_code - Get exit code from CP boot rom download app
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: exit code from CP boot rom download APP
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*/
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enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_exec_stage - Query CP execution stage
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: CP execution stage
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*/
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enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_get_ipc_state - Query CP IPC state
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* @ipc_mmio: Pointer to mmio instance
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*
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* Returns: CP IPC state
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*/
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enum ipc_mem_device_ipc_state
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ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_copy_chip_info - Copy size bytes of CP chip info structure
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* into caller provided buffer
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* @ipc_mmio: Pointer to mmio instance
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* @dest: Pointer to caller provided buff
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* @size: Number of bytes to copy
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*/
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void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,
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size_t size);
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/**
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* ipc_mmio_config - Write context info and AP memory range addresses.
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* This needs to be called when CP is in
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* IPC_MEM_DEVICE_IPC_INIT state
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*
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* @ipc_mmio: Pointer to mmio instance
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*/
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void ipc_mmio_config(struct iosm_mmio *ipc_mmio);
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/**
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* ipc_mmio_update_cp_capability - Read and update modem capability, from mmio
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* capability offset
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*
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* @ipc_mmio: Pointer to mmio instance
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*/
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void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio);
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#endif
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