drm/amd/display: add max scl ratio to soc bounding box

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-06-28 12:28:00 -04:00 committed by Alex Deucher
parent ece4147fea
commit dbcac9c8ab

View File

@ -111,6 +111,8 @@ struct _vcs_dpi_soc_bounding_box_st {
double xfc_bus_transport_time_us;
double xfc_xbuf_latency_tolerance_us;
int use_urgent_burst_bw;
double max_hscl_ratio;
double max_vscl_ratio;
struct _vcs_dpi_voltage_scaling_st clock_limits[7];
};