From 9f5ce88de82cd71024b657f069342533af3378b4 Mon Sep 17 00:00:00 2001 From: Zhou Wang Date: Mon, 14 Aug 2017 17:23:48 +0800 Subject: [PATCH 01/13] arm64: dts: hisi: add PCIe host controller node for hip07 SoC Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in D05 board. Signed-off-by: Zhou Wang Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 4 ++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 22 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index f5d7f0889b41..fe7c16c36025 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -84,3 +84,7 @@ &sas1 { status = "ok"; }; + +&p0_pcie2_a { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 283d7b532e16..2c01a21c3665 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1534,5 +1534,27 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + p0_pcie2_a: pcie@a00a0000 { + compatible = "hisilicon,hip07-pcie-ecam"; + reg = <0 0xaf800000 0 0x800000>, + <0 0xa00a0000 0 0x10000>; + bus-range = <0xf8 0xff>; + msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 + 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 + 0x0 0 0 2 &mbigen_pcie2_a 671 4 + 0x0 0 0 3 &mbigen_pcie2_a 671 4 + 0x0 0 0 4 &mbigen_pcie2_a 671 4>; + status = "disabled"; + }; }; }; From 94d2d94b40ca88b558af8a1d4b091f5027efb271 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 16 Aug 2017 15:26:35 +0800 Subject: [PATCH 02/13] arm64: dts: hi6220: add acpu_sctrl Add acpu_sctrl clock node Signed-off-by: Zhangfei Gao Signed-off-by: Li Pengcheng Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index eacbe0db5bc2..f8012d51400a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -262,6 +262,12 @@ #clock-cells = <1>; }; + acpu_sctrl: acpu_sctrl@f6504000 { + compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; + reg = <0x0 0xf6504000 0x0 0x1000>; + #clock-cells = <1>; + }; + medianoc_ade: medianoc_ade@f4520000 { compatible = "syscon"; reg = <0x0 0xf4520000 0x0 0x4000>; From 341b26b719c89faa59013cf0f5aaab624b49d613 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 7 Aug 2017 13:01:29 +0800 Subject: [PATCH 03/13] arm64: dts: hi6220: improve g-tx-fifo-size setting for usb device The current usb device g-tx-fifo-size setting in DT causes two problems for kernel driver. 1. On hi6220, there are 15 tx_fifo dedicated for all EPs except EP0, while DT only provides tx_fifo settings for 6 EPs. It results in the following annoying complaints from kernel. [ 4.451623] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[7]=0 [ 4.461303] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[8]=0 [ 4.470969] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[9]=0 [ 4.480632] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[10]=0 [ 4.490385] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[11]=0 [ 4.500140] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[12]=0 [ 4.509892] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[13]=0 [ 4.519646] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[14]=0 [ 4.529399] dwc2 f72c0000.usb: dwc2_check_param_tx_fifo_sizes: Invalid parameter g_tx_fifo_size[15]=0 [ 4.539244] dwc2 f72c0000.usb: EPs: 16, dedicated fifos, 1920 entries in SPRAM Besides of that, the total 1920 fifo entries isn't fully utilized. Endpoint Info Control block consumes 128 entries, g-rx-fifo-size is 512, and g-np-tx-fifo-size is 128. So the fifi entries available for tx_fifo is: 1920 - 128 - 512 - 128 = 1152. Considering that the minimal valid tx_fifo size for each EP is 16, it should be reasonable to allocate 1152 entries as: 128 x 8 + 16 x 7 = 1136 (only 16 entries unused). With this new setting, we can get more EPs to use while removing the above warning messages in the meantime. 2. Another consequence of above invalid g_tx_fifo_size parameter is that kernel driver will use values read from hardware register as the fall-back. The value is 2048 for each EP fifo. That's obviously invalid either, because even fifo entries for one EP exceeds the total entries 1920. That's why we see the following fat warning from function dwc2_hsotg_init_fifo(). The new g-tx-fifo-size settings help to remove the warning as well. [ 65.431634] dwc2 f72c0000.usb: Do port resume before switching to device mode [ 65.624176] insufficient fifo memory [ 65.624369] ------------[ cut here ]------------ [ 65.633633] WARNING: CPU: 0 PID: 5 at drivers/usb/dwc2/gadget.c:330 dwc2_hsotg_init_fifo+0x164/0x1ac [ 65.643808] CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.13.0-rc1-00022-g50861cf9dc1b-dirty #81 [ 65.653769] Hardware name: HiKey Development Board (DT) [ 65.659624] Workqueue: dwc2 dwc2_conn_id_status_change [ 65.665377] task: ffffffc005f73400 task.stack: ffffffc005f98000 [ 65.671987] PC is at dwc2_hsotg_init_fifo+0x164/0x1ac [ 65.677633] LR is at dwc2_hsotg_init_fifo+0x164/0x1ac [ 65.683275] pc : [] lr : [] pstate: 600001c5 [ 65.691504] sp : ffffffc005f9bce0 [ 65.695218] x29: ffffffc005f9bce0 x28: ffffffc005f6ac00 [ 65.701172] x27: ffffffc005f73400 x26: 0000000008000580 [ 65.707124] x25: ffffff8008bb4af0 x24: ffffff8008d02b70 [ 65.713074] x23: 0000003fcc831084 x22: ffffffc0337cf0bc [ 65.719024] x21: 0000000000000580 x20: ffffffc0337cf018 [ 65.724976] x19: ffffffc0337cf098 x18: 0000000000000000 [ 65.730926] x17: 0000000000000000 x16: 0000000000000000 [ 65.736873] x15: 0000000000000000 x14: ffffff8008ca8900 [ 65.742825] x13: 0000004035299000 x12: 0000000034d5d91d [ 65.748775] x11: 0000000000000000 x10: 00000000000008d0 [ 65.754726] x9 : ffffffc005f9bce0 x8 : 00000000000001b5 [ 65.760674] x7 : 66696620746e6569 x6 : ffffff8008d60050 [ 65.766623] x5 : 0000000000000000 x4 : 0000000000000000 [ 65.772573] x3 : 0000000000000002 x2 : 0000000000000002 [ 65.778521] x1 : 0000000000000001 x0 : 0000000000000018 [ 65.784469] Call trace: [ 65.787236] Exception stack(0xffffffc005f9bb10 to 0xffffffc005f9bc40) [ 65.794420] bb00: ffffffc0337cf098 0000008000000000 [ 65.803145] bb20: ffffffc005f9bce0 ffffff8008638044 ffffff8008bb4af0 0000000008000580 [ 65.811870] bb40: ffffffc005f73400 ffffffc005f6ac00 0000000000000000 ffffff8008da2998 [ 65.820595] bb60: ffffffc005f9bce0 ffffffc005f9bce0 ffffffc005f9bca0 00000000ffffffc8 [ 65.829315] bb80: ffffffc005f9bbb0 ffffff80081046a0 ffffffc005f9bce0 ffffffc005f9bce0 [ 65.838038] bba0: ffffffc005f9bca0 00000000ffffffc8 0000000000000018 0000000000000001 [ 65.846761] bbc0: 0000000000000002 0000000000000002 0000000000000000 0000000000000000 [ 65.855485] bbe0: ffffff8008d60050 66696620746e6569 00000000000001b5 ffffffc005f9bce0 [ 65.864207] bc00: 00000000000008d0 0000000000000000 0000000034d5d91d 0000004035299000 [ 65.872928] bc20: ffffff8008ca8900 0000000000000000 0000000000000000 0000000000000000 [ 65.900856] [] dwc2_hsotg_init_fifo+0x164/0x1ac [ 65.927195] [] dwc2_hsotg_core_init_disconnected+0x80/0x3c0 [ 65.954736] [] dwc2_conn_id_status_change+0xfc/0x21c [ 65.981561] [] process_one_work+0x124/0x294 [ 66.007419] [] worker_thread+0x58/0x3c8 [ 66.023243] [] kthread+0x100/0x12c [ 66.032455] [] ret_from_fork+0x10/0x50 [ 66.041987] ---[ end trace 7079dcaa2d9e46fa ]--- Signed-off-by: Shawn Guo Tested-by: John Stultz Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f8012d51400a..02a3aa4b2165 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -761,7 +761,8 @@ dr_mode = "otg"; g-rx-fifo-size = <512>; g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 128 128 128 128>; + g-tx-fifo-size = <128 128 128 128 128 128 128 128 + 16 16 16 16 16 16 16>; interrupts = <0 77 0x4>; }; From 30fec8268cc1d6501815f4fff44ec9fe412933b0 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 14 Aug 2017 17:50:40 +0800 Subject: [PATCH 04/13] arm64: dts: hi3660: enable idle states There are two clusters on the Hi3660, the first one is Cortex-A53 based and the other one is Cortex-A73 based. These two clusters have different idle states. Thanks to Daniel Lezcano's recent changes, the generic ARM cpuidle driver can now support several clusters with different idle states, thus supporting the big.Little architecture. In addition to the WFI idle state which is the default shallowest state for all ARM cpus, the Hi3660 supports the following states: - CA53 CPUs: - CPU_SLEEP: CPU power off state - CLUSTER_SLEEP_0: Cluster power off state - CA73 CPUs: - CPU_NAP: CPU retention state - CPU_SLEEP: CPU power off state - CLUSTER_SLEEP_1: Cluster power off state This patch adds the idle states description for the Hi3660 to the device tree. Cc: Kevin Wang Signed-off-by: Leo Yan Acked-by: Daniel Lezcano Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index c6a1961e8d55..8921310e4c55 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -58,6 +58,7 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu1: cpu@1 { @@ -65,6 +66,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu2: cpu@2 { @@ -72,6 +74,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu3: cpu@3 { @@ -79,6 +82,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; cpu4: cpu@100 { @@ -86,6 +90,11 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu5: cpu@101 { @@ -93,6 +102,11 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu6: cpu@102 { @@ -100,6 +114,11 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; }; cpu7: cpu@103 { @@ -107,6 +126,50 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + }; + + idle-states { + entry-method = "psci"; + + CPU_NAP: cpu-nap { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <7>; + exit-latency-us = <2>; + min-residency-us = <15>; + }; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <70>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; }; }; From a6d083441cd3a5ad1645593c00c37e73b536bd74 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 14 Aug 2017 17:50:41 +0800 Subject: [PATCH 05/13] arm64: dts: hi3660: add L2 cache topology This patch adds the L2 cache topology on 96boards Hikey960. Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8921310e4c55..1cdd03b5d1b3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -58,6 +58,7 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -66,6 +67,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -74,6 +76,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -82,6 +85,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -90,6 +94,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -102,6 +107,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -114,6 +120,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -126,6 +133,7 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -171,6 +179,14 @@ min-residency-us = <20000>; }; }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A73_L2: l2-cache1 { + compatible = "cache"; + }; }; gic: interrupt-controller@e82b0000 { From f8054fb8a734ac2745ba6e8960a02bff0ccc20c7 Mon Sep 17 00:00:00 2001 From: YiPing Xu Date: Mon, 14 Aug 2017 17:50:42 +0800 Subject: [PATCH 06/13] arm64: dts: hi3660: add pmu dt node for hi3660 Add pmu dt node for hi3660 Signed-off-by: YiPing Xu Signed-off-by: Zhong Kaihua Signed-off-by: Leo Yan Tested-by: Jumana Mundichipparakkal Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 1cdd03b5d1b3..5fd56862e7fc 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -202,6 +202,26 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>, + <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; From 313aebda8432afd98ff1663cbc62f2c35245a006 Mon Sep 17 00:00:00 2001 From: Victor Chong Date: Mon, 14 Aug 2017 17:50:43 +0800 Subject: [PATCH 07/13] arm64: dts: hikey960: Add optee node This patch adds op-tee node for hikey960 Signed-off-by: Victor Chong Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 6609b0fe7a8b..b96d865649a0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -159,6 +159,13 @@ startup-delay-us = <70000>; enable-active-high; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &i2c0 { From b6b681c1442e0f5485e4d6d1b427c63ddc66ae93 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 14 Aug 2017 17:50:44 +0800 Subject: [PATCH 08/13] arm64: dts: hikey960: Add support for syscon-reboot-mode Add support to hikey960 dts for the syscon-reboot-mode driver. Cc: John Stultz Signed-off-by: Guodong Xu Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index b96d865649a0..ce5e8747219e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -39,6 +39,20 @@ reg = <0x0 0x0 0x0 0x0>; }; + reboot-mode-syscon@32100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x32100000 0x0 0x00001000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; + keys { compatible = "gpio-keys"; pinctrl-names = "default"; From 9c24dc9d00ee68270a8cd8ef1a8fc127ba616ea8 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 14 Aug 2017 17:50:45 +0800 Subject: [PATCH 09/13] arm64: dts: hikey960: Add pstore support This patch reserves some memory in the DTS and sets up a pstore device tree node to enable pstore support on HiKey960. Cc: John Stultz Signed-off-by: Guodong Xu Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index ce5e8747219e..7770ec7c566a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -39,6 +39,20 @@ reg = <0x0 0x0 0x0 0x0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@32000000 { + compatible = "ramoops"; + reg = <0x0 0x32000000 0x0 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + reboot-mode-syscon@32100000 { compatible = "syscon", "simple-mfd"; reg = <0x0 0x32100000 0x0 0x00001000>; From 996707d765d8646ecf278447f3b2cf1c7faa81e0 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 14 Aug 2017 17:50:46 +0800 Subject: [PATCH 10/13] arm64: dts: hi3660: Reset the mmc hosts Add reset-names = "reset" into mmc nodes. Signed-off-by: Guodong Xu Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 5fd56862e7fc..41841f7ca71b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -909,6 +909,7 @@ clock-names = "ciu", "biu"; clock-frequency = <3200000>; resets = <&crg_rst 0x94 18>; + reset-names = "reset"; cd-gpios = <&gpio25 3 0>; hisilicon,peripheral-syscon = <&sctrl>; pinctrl-names = "default"; @@ -938,6 +939,7 @@ <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; clock-names = "ciu", "biu"; resets = <&crg_rst 0x94 20>; + reset-names = "reset"; card-detect-delay = <200>; supports-highspeed; keep-power-in-suspend; From bf1ff5328a8833ca9ffebad9081fd303a867117f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 14 Aug 2017 17:50:47 +0800 Subject: [PATCH 11/13] arm64: dts: hikey960: change bluetooth uart max-speed to 3mbps Update bluetooth UART max-speed to 3Mbps Signed-off-by: Guodong Xu Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 7770ec7c566a..fd4705c451e2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -230,7 +230,7 @@ bluetooth { compatible = "ti,wl1837-st"; enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; - max-speed = <921600>; + max-speed = <3000000>; }; }; From 0b507e91de1e18c7e934dd585459b07935ed8c23 Mon Sep 17 00:00:00 2001 From: Wang Ruyi Date: Mon, 14 Aug 2017 17:50:48 +0800 Subject: [PATCH 12/13] arm64: dts: hi3660: add bindings for DMA Add bindings for DMA. Signed-off-by: Wang Ruyi Signed-off-by: Guodong Xu Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 41841f7ca71b..545d435d11b3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -436,6 +436,19 @@ status = "disabled"; }; + dma0: dma@fdf30000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0x0 0xfdf30000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <32>; + dma-min-chan = <1>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; + dma-no-cci; + dma-type = "hi3660_dma"; + }; + rtc0: rtc@fff04000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0Xfff04000 0x0 0x1000>; From 487f00d4b95e086f89d65f7024b71d81628f1551 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 14 Aug 2017 17:50:49 +0800 Subject: [PATCH 13/13] arm64: dts: hi3660: enable watchdog This patch is to add watchdog binding for Hi3660 on Hikey960 board. Cc: Guodong Xu Cc: Zhong Kaihua Signed-off-by: Leo Yan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 545d435d11b3..b7a90d632959 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -962,5 +962,21 @@ &sdio_cfg_func>; status = "disabled"; }; + + watchdog0: watchdog@e8a06000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a06000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; + + watchdog1: watchdog@e8a07000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a07000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; }; };