Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next
- Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Fixes for clk controllers on qcom msm8998 SoCs - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Adjust composite clk to new way of describing clk parents - Add a driver for BCLK of Freescale SAI cores * clk-imx: (32 commits) clk: imx: Add support for i.MX8MP clock driver dt-bindings: imx: Add clock binding doc for i.MX8MP clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API clk: imx: imx8mq: Switch to clk_hw based API clk: imx: imx8mm: Switch to clk_hw based API clk: imx: imx8mn: Switch to clk_hw based API clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API clk: imx: gate3: Switch to clk_hw based API clk: imx: add hw API imx_clk_hw_mux2_flags clk: imx: add imx_unregister_hw_clocks clk: imx: clk-composite-8m: Switch to clk_hw based API clk: imx: clk-pll14xx: Switch to clk_hw based API clk: imx7up: Rename the clks to hws clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based clk: imx: Rename sccg and frac pll register to suggest clk_hw clk: imx: imx7ulp composite: Rename to show is clk_hw based clk: imx: pllv2: Switch to clk_hw based API clk: imx: pllv1: Switch to clk_hw based API ... * clk-ti: clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock * clk-xilinx: clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver * clk-nvidia: clk: tegra20/30: Explicitly set parent clock for Video Decoder clk: tegra20/30: Don't pre-initialize displays parent clock clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() clk: tegra: Mark fuse clock as critical * clk-qcom: (35 commits) clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: qcom: Add ipq6018 Global Clock Controller support clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks clk: qcom: rpmh: Add IPA clock for SC7180 clk: qcom: rpmh: skip undefined clocks when registering clk: qcom: Add video clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings clk: qcom: Add graphics clock controller driver for SC7180 dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent clk: qcom: Add display clock controller driver for SC7180 dt-bindings: clock: Introduce QCOM sc7180 display clock bindings dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration clk: qcom: alpha-pll: Remove useless read from set rate ... * clk-freescale: clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants * clk-qoriq: clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
This commit is contained in:
Stephen Boyd
@@ -29,6 +29,16 @@
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#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
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#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
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/* vip clocks */
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#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
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/* vpe clocks */
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#define DRA7_VPE_CLKCTRL_OFFSET 0x60
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#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
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#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
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/* coreaon clocks */
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#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
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@@ -78,6 +88,9 @@
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#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
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/* gpu clocks */
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#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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/* l3init clocks */
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#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
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@@ -192,6 +205,16 @@
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/* rtc clocks */
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#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
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/* vip clocks */
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#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
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/* vpe clocks */
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#define DRA7_VPE_CLKCTRL_OFFSET 0x60
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#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
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#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
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/* coreaon clocks */
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#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
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300
include/dt-bindings/clock/imx8mp-clock.h
Normal file
300
include/dt-bindings/clock/imx8mp-clock.h
Normal file
@@ -0,0 +1,300 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
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#define __DT_BINDINGS_CLOCK_IMX8MP_H
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#define IMX8MP_CLK_DUMMY 0
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#define IMX8MP_CLK_32K 1
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#define IMX8MP_CLK_24M 2
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#define IMX8MP_OSC_HDMI_CLK 3
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#define IMX8MP_CLK_EXT1 4
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#define IMX8MP_CLK_EXT2 5
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#define IMX8MP_CLK_EXT3 6
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#define IMX8MP_CLK_EXT4 7
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#define IMX8MP_AUDIO_PLL1_REF_SEL 8
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#define IMX8MP_AUDIO_PLL2_REF_SEL 9
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#define IMX8MP_VIDEO_PLL1_REF_SEL 10
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#define IMX8MP_DRAM_PLL_REF_SEL 11
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#define IMX8MP_GPU_PLL_REF_SEL 12
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#define IMX8MP_VPU_PLL_REF_SEL 13
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#define IMX8MP_ARM_PLL_REF_SEL 14
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#define IMX8MP_SYS_PLL1_REF_SEL 15
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#define IMX8MP_SYS_PLL2_REF_SEL 16
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#define IMX8MP_SYS_PLL3_REF_SEL 17
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#define IMX8MP_AUDIO_PLL1 18
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#define IMX8MP_AUDIO_PLL2 19
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#define IMX8MP_VIDEO_PLL1 20
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#define IMX8MP_DRAM_PLL 21
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#define IMX8MP_GPU_PLL 22
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#define IMX8MP_VPU_PLL 23
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#define IMX8MP_ARM_PLL 24
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#define IMX8MP_SYS_PLL1 25
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#define IMX8MP_SYS_PLL2 26
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#define IMX8MP_SYS_PLL3 27
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#define IMX8MP_AUDIO_PLL1_BYPASS 28
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#define IMX8MP_AUDIO_PLL2_BYPASS 29
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#define IMX8MP_VIDEO_PLL1_BYPASS 30
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#define IMX8MP_DRAM_PLL_BYPASS 31
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#define IMX8MP_GPU_PLL_BYPASS 32
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#define IMX8MP_VPU_PLL_BYPASS 33
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#define IMX8MP_ARM_PLL_BYPASS 34
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#define IMX8MP_SYS_PLL1_BYPASS 35
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#define IMX8MP_SYS_PLL2_BYPASS 36
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#define IMX8MP_SYS_PLL3_BYPASS 37
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#define IMX8MP_AUDIO_PLL1_OUT 38
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#define IMX8MP_AUDIO_PLL2_OUT 39
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#define IMX8MP_VIDEO_PLL1_OUT 40
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#define IMX8MP_DRAM_PLL_OUT 41
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#define IMX8MP_GPU_PLL_OUT 42
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#define IMX8MP_VPU_PLL_OUT 43
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#define IMX8MP_ARM_PLL_OUT 44
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#define IMX8MP_SYS_PLL1_OUT 45
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#define IMX8MP_SYS_PLL2_OUT 46
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#define IMX8MP_SYS_PLL3_OUT 47
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#define IMX8MP_SYS_PLL1_40M 48
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#define IMX8MP_SYS_PLL1_80M 49
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#define IMX8MP_SYS_PLL1_100M 50
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#define IMX8MP_SYS_PLL1_133M 51
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#define IMX8MP_SYS_PLL1_160M 52
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#define IMX8MP_SYS_PLL1_200M 53
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#define IMX8MP_SYS_PLL1_266M 54
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#define IMX8MP_SYS_PLL1_400M 55
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#define IMX8MP_SYS_PLL1_800M 56
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#define IMX8MP_SYS_PLL2_50M 57
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#define IMX8MP_SYS_PLL2_100M 58
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#define IMX8MP_SYS_PLL2_125M 59
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#define IMX8MP_SYS_PLL2_166M 60
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#define IMX8MP_SYS_PLL2_200M 61
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#define IMX8MP_SYS_PLL2_250M 62
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#define IMX8MP_SYS_PLL2_333M 63
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#define IMX8MP_SYS_PLL2_500M 64
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#define IMX8MP_SYS_PLL2_1000M 65
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#define IMX8MP_CLK_A53_SRC 66
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#define IMX8MP_CLK_M7_SRC 67
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#define IMX8MP_CLK_ML_SRC 68
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#define IMX8MP_CLK_GPU3D_CORE_SRC 69
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#define IMX8MP_CLK_GPU3D_SHADER_SRC 70
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#define IMX8MP_CLK_GPU2D_SRC 71
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#define IMX8MP_CLK_AUDIO_AXI_SRC 72
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#define IMX8MP_CLK_HSIO_AXI_SRC 73
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#define IMX8MP_CLK_MEDIA_ISP_SRC 74
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#define IMX8MP_CLK_A53_CG 75
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#define IMX8MP_CLK_M4_CG 76
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#define IMX8MP_CLK_ML_CG 77
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#define IMX8MP_CLK_GPU3D_CORE_CG 78
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#define IMX8MP_CLK_GPU3D_SHADER_CG 79
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#define IMX8MP_CLK_GPU2D_CG 80
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#define IMX8MP_CLK_AUDIO_AXI_CG 81
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#define IMX8MP_CLK_HSIO_AXI_CG 82
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#define IMX8MP_CLK_MEDIA_ISP_CG 83
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#define IMX8MP_CLK_A53_DIV 84
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#define IMX8MP_CLK_M7_DIV 85
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#define IMX8MP_CLK_ML_DIV 86
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#define IMX8MP_CLK_GPU3D_CORE_DIV 87
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#define IMX8MP_CLK_GPU3D_SHADER_DIV 88
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#define IMX8MP_CLK_GPU2D_DIV 89
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#define IMX8MP_CLK_AUDIO_AXI_DIV 90
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#define IMX8MP_CLK_HSIO_AXI_DIV 91
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#define IMX8MP_CLK_MEDIA_ISP_DIV 92
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#define IMX8MP_CLK_MAIN_AXI 93
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#define IMX8MP_CLK_ENET_AXI 94
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#define IMX8MP_CLK_NAND_USDHC_BUS 95
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#define IMX8MP_CLK_VPU_BUS 96
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#define IMX8MP_CLK_MEDIA_AXI 97
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#define IMX8MP_CLK_MEDIA_APB 98
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#define IMX8MP_CLK_HDMI_APB 99
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#define IMX8MP_CLK_HDMI_AXI 100
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#define IMX8MP_CLK_GPU_AXI 101
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#define IMX8MP_CLK_GPU_AHB 102
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#define IMX8MP_CLK_NOC 103
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#define IMX8MP_CLK_NOC_IO 104
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#define IMX8MP_CLK_ML_AXI 105
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#define IMX8MP_CLK_ML_AHB 106
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#define IMX8MP_CLK_AHB 107
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#define IMX8MP_CLK_AUDIO_AHB 108
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#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
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#define IMX8MP_CLK_IPG_ROOT 110
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#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
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#define IMX8MP_CLK_DRAM_ALT 112
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#define IMX8MP_CLK_DRAM_APB 113
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#define IMX8MP_CLK_VPU_G1 114
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#define IMX8MP_CLK_VPU_G2 115
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#define IMX8MP_CLK_CAN1 116
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#define IMX8MP_CLK_CAN2 117
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#define IMX8MP_CLK_MEMREPAIR 118
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#define IMX8MP_CLK_PCIE_PHY 119
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#define IMX8MP_CLK_PCIE_AUX 120
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#define IMX8MP_CLK_I2C5 121
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#define IMX8MP_CLK_I2C6 122
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#define IMX8MP_CLK_SAI1 123
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#define IMX8MP_CLK_SAI2 124
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#define IMX8MP_CLK_SAI3 125
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#define IMX8MP_CLK_SAI4 126
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#define IMX8MP_CLK_SAI5 127
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#define IMX8MP_CLK_SAI6 128
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#define IMX8MP_CLK_ENET_QOS 129
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#define IMX8MP_CLK_ENET_QOS_TIMER 130
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#define IMX8MP_CLK_ENET_REF 131
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#define IMX8MP_CLK_ENET_TIMER 132
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#define IMX8MP_CLK_ENET_PHY_REF 133
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#define IMX8MP_CLK_NAND 134
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#define IMX8MP_CLK_QSPI 135
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#define IMX8MP_CLK_USDHC1 136
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#define IMX8MP_CLK_USDHC2 137
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#define IMX8MP_CLK_I2C1 138
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#define IMX8MP_CLK_I2C2 139
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#define IMX8MP_CLK_I2C3 140
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#define IMX8MP_CLK_I2C4 141
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#define IMX8MP_CLK_UART1 142
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#define IMX8MP_CLK_UART2 143
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#define IMX8MP_CLK_UART3 144
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#define IMX8MP_CLK_UART4 145
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#define IMX8MP_CLK_USB_CORE_REF 146
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#define IMX8MP_CLK_USB_PHY_REF 147
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#define IMX8MP_CLK_GIC 148
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#define IMX8MP_CLK_ECSPI1 149
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#define IMX8MP_CLK_ECSPI2 150
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#define IMX8MP_CLK_PWM1 151
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#define IMX8MP_CLK_PWM2 152
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#define IMX8MP_CLK_PWM3 153
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#define IMX8MP_CLK_PWM4 154
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#define IMX8MP_CLK_GPT1 155
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#define IMX8MP_CLK_GPT2 156
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#define IMX8MP_CLK_GPT3 157
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#define IMX8MP_CLK_GPT4 158
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#define IMX8MP_CLK_GPT5 159
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#define IMX8MP_CLK_GPT6 160
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#define IMX8MP_CLK_TRACE 161
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#define IMX8MP_CLK_WDOG 162
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#define IMX8MP_CLK_WRCLK 163
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#define IMX8MP_CLK_IPP_DO_CLKO1 164
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#define IMX8MP_CLK_IPP_DO_CLKO2 165
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#define IMX8MP_CLK_HDMI_FDCC_TST 166
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#define IMX8MP_CLK_HDMI_27M 167
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#define IMX8MP_CLK_HDMI_REF_266M 168
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#define IMX8MP_CLK_USDHC3 169
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#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
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#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
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#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
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#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
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#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174
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#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
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#define IMX8MP_CLK_PCIE2_CTRL 176
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#define IMX8MP_CLK_PCIE2_PHY 177
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#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
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#define IMX8MP_CLK_ECSPI3 179
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#define IMX8MP_CLK_PDM 180
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#define IMX8MP_CLK_VPU_VC8000E 181
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#define IMX8MP_CLK_SAI7 182
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#define IMX8MP_CLK_GPC_ROOT 183
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#define IMX8MP_CLK_ANAMIX_ROOT 184
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#define IMX8MP_CLK_CPU_ROOT 185
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#define IMX8MP_CLK_CSU_ROOT 186
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#define IMX8MP_CLK_DEBUG_ROOT 187
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#define IMX8MP_CLK_DRAM1_ROOT 188
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#define IMX8MP_CLK_ECSPI1_ROOT 189
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#define IMX8MP_CLK_ECSPI2_ROOT 190
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#define IMX8MP_CLK_ECSPI3_ROOT 191
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#define IMX8MP_CLK_ENET1_ROOT 192
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#define IMX8MP_CLK_GPIO1_ROOT 193
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#define IMX8MP_CLK_GPIO2_ROOT 194
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#define IMX8MP_CLK_GPIO3_ROOT 195
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#define IMX8MP_CLK_GPIO4_ROOT 196
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#define IMX8MP_CLK_GPIO5_ROOT 197
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#define IMX8MP_CLK_GPT1_ROOT 198
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#define IMX8MP_CLK_GPT2_ROOT 199
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#define IMX8MP_CLK_GPT3_ROOT 200
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#define IMX8MP_CLK_GPT4_ROOT 201
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#define IMX8MP_CLK_GPT5_ROOT 202
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#define IMX8MP_CLK_GPT6_ROOT 203
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#define IMX8MP_CLK_HS_ROOT 204
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#define IMX8MP_CLK_I2C1_ROOT 205
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#define IMX8MP_CLK_I2C2_ROOT 206
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#define IMX8MP_CLK_I2C3_ROOT 207
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#define IMX8MP_CLK_I2C4_ROOT 208
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#define IMX8MP_CLK_IOMUX_ROOT 209
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#define IMX8MP_CLK_IPMUX1_ROOT 210
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#define IMX8MP_CLK_IPMUX2_ROOT 211
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#define IMX8MP_CLK_IPMUX3_ROOT 212
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#define IMX8MP_CLK_MU_ROOT 213
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#define IMX8MP_CLK_OCOTP_ROOT 214
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#define IMX8MP_CLK_OCRAM_ROOT 215
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#define IMX8MP_CLK_OCRAM_S_ROOT 216
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#define IMX8MP_CLK_PCIE_ROOT 217
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#define IMX8MP_CLK_PERFMON1_ROOT 218
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#define IMX8MP_CLK_PERFMON2_ROOT 219
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#define IMX8MP_CLK_PWM1_ROOT 220
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#define IMX8MP_CLK_PWM2_ROOT 221
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#define IMX8MP_CLK_PWM3_ROOT 222
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#define IMX8MP_CLK_PWM4_ROOT 223
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#define IMX8MP_CLK_QOS_ROOT 224
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#define IMX8MP_CLK_QOS_ENET_ROOT 225
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#define IMX8MP_CLK_QSPI_ROOT 226
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#define IMX8MP_CLK_NAND_ROOT 227
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#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
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#define IMX8MP_CLK_RDC_ROOT 229
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#define IMX8MP_CLK_ROM_ROOT 230
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#define IMX8MP_CLK_I2C5_ROOT 231
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#define IMX8MP_CLK_I2C6_ROOT 232
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#define IMX8MP_CLK_CAN1_ROOT 233
|
||||
#define IMX8MP_CLK_CAN2_ROOT 234
|
||||
#define IMX8MP_CLK_SCTR_ROOT 235
|
||||
#define IMX8MP_CLK_SDMA1_ROOT 236
|
||||
#define IMX8MP_CLK_ENET_QOS_ROOT 237
|
||||
#define IMX8MP_CLK_SEC_DEBUG_ROOT 238
|
||||
#define IMX8MP_CLK_SEMA1_ROOT 239
|
||||
#define IMX8MP_CLK_SEMA2_ROOT 240
|
||||
#define IMX8MP_CLK_IRQ_STEER_ROOT 241
|
||||
#define IMX8MP_CLK_SIM_ENET_ROOT 242
|
||||
#define IMX8MP_CLK_SIM_M_ROOT 243
|
||||
#define IMX8MP_CLK_SIM_MAIN_ROOT 244
|
||||
#define IMX8MP_CLK_SIM_S_ROOT 245
|
||||
#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
|
||||
#define IMX8MP_CLK_GPU2D_ROOT 247
|
||||
#define IMX8MP_CLK_GPU3D_ROOT 248
|
||||
#define IMX8MP_CLK_SNVS_ROOT 249
|
||||
#define IMX8MP_CLK_TRACE_ROOT 250
|
||||
#define IMX8MP_CLK_UART1_ROOT 251
|
||||
#define IMX8MP_CLK_UART2_ROOT 252
|
||||
#define IMX8MP_CLK_UART3_ROOT 253
|
||||
#define IMX8MP_CLK_UART4_ROOT 254
|
||||
#define IMX8MP_CLK_USB_ROOT 255
|
||||
#define IMX8MP_CLK_USB_PHY_ROOT 256
|
||||
#define IMX8MP_CLK_USDHC1_ROOT 257
|
||||
#define IMX8MP_CLK_USDHC2_ROOT 258
|
||||
#define IMX8MP_CLK_WDOG1_ROOT 259
|
||||
#define IMX8MP_CLK_WDOG2_ROOT 260
|
||||
#define IMX8MP_CLK_WDOG3_ROOT 261
|
||||
#define IMX8MP_CLK_VPU_G1_ROOT 262
|
||||
#define IMX8MP_CLK_GPU_ROOT 263
|
||||
#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
|
||||
#define IMX8MP_CLK_VPU_VC8KE_ROOT 265
|
||||
#define IMX8MP_CLK_VPU_G2_ROOT 266
|
||||
#define IMX8MP_CLK_NPU_ROOT 267
|
||||
#define IMX8MP_CLK_HSIO_ROOT 268
|
||||
#define IMX8MP_CLK_MEDIA_APB_ROOT 269
|
||||
#define IMX8MP_CLK_MEDIA_AXI_ROOT 270
|
||||
#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
|
||||
#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
|
||||
#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
|
||||
#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
|
||||
#define IMX8MP_CLK_MEDIA_ISP_ROOT 276
|
||||
#define IMX8MP_CLK_USDHC3_ROOT 277
|
||||
#define IMX8MP_CLK_HDMI_ROOT 278
|
||||
#define IMX8MP_CLK_XTAL_ROOT 279
|
||||
#define IMX8MP_CLK_PLL_ROOT 280
|
||||
#define IMX8MP_CLK_TSENSOR_ROOT 281
|
||||
#define IMX8MP_CLK_VPU_ROOT 282
|
||||
#define IMX8MP_CLK_MRPR_ROOT 283
|
||||
#define IMX8MP_CLK_AUDIO_ROOT 284
|
||||
#define IMX8MP_CLK_DRAM_ALT_ROOT 285
|
||||
#define IMX8MP_CLK_DRAM_CORE 286
|
||||
#define IMX8MP_CLK_ARM 287
|
||||
|
||||
#define IMX8MP_CLK_END 288
|
||||
|
||||
#endif
|
||||
@@ -16,6 +16,7 @@
|
||||
|
||||
/* abe clocks */
|
||||
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
|
||||
|
||||
46
include/dt-bindings/clock/qcom,dispcc-sc7180.h
Normal file
46
include/dt-bindings/clock/qcom,dispcc-sc7180.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
|
||||
|
||||
#define DISP_CC_PLL0 0
|
||||
#define DISP_CC_PLL0_OUT_EVEN 1
|
||||
#define DISP_CC_MDSS_AHB_CLK 2
|
||||
#define DISP_CC_MDSS_AHB_CLK_SRC 3
|
||||
#define DISP_CC_MDSS_BYTE0_CLK 4
|
||||
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
|
||||
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK 8
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK 10
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK 12
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
|
||||
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
|
||||
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK 16
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
|
||||
#define DISP_CC_MDSS_ESC0_CLK 18
|
||||
#define DISP_CC_MDSS_ESC0_CLK_SRC 19
|
||||
#define DISP_CC_MDSS_MDP_CLK 20
|
||||
#define DISP_CC_MDSS_MDP_CLK_SRC 21
|
||||
#define DISP_CC_MDSS_MDP_LUT_CLK 22
|
||||
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
|
||||
#define DISP_CC_MDSS_PCLK0_CLK 24
|
||||
#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
|
||||
#define DISP_CC_MDSS_ROT_CLK 26
|
||||
#define DISP_CC_MDSS_ROT_CLK_SRC 27
|
||||
#define DISP_CC_MDSS_RSCC_AHB_CLK 28
|
||||
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
|
||||
#define DISP_CC_MDSS_VSYNC_CLK 30
|
||||
#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
|
||||
#define DISP_CC_XO_CLK 32
|
||||
|
||||
/* DISP_CC GDSCR */
|
||||
#define MDSS_GDSC 0
|
||||
|
||||
#endif
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
|
||||
@@ -35,6 +35,17 @@
|
||||
#define DISP_CC_PLL0 25
|
||||
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
|
||||
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK 28
|
||||
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK 30
|
||||
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK 32
|
||||
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33
|
||||
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34
|
||||
#define DISP_CC_MDSS_DP_PIXEL1_CLK 35
|
||||
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK 37
|
||||
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38
|
||||
|
||||
/* DISP_CC Reset */
|
||||
#define DISP_CC_MDSS_RSCC_BCR 0
|
||||
|
||||
262
include/dt-bindings/clock/qcom,gcc-ipq6018.h
Normal file
262
include/dt-bindings/clock/qcom,gcc-ipq6018.h
Normal file
@@ -0,0 +1,262 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
|
||||
#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
|
||||
|
||||
#define GPLL0 0
|
||||
#define UBI32_PLL 1
|
||||
#define GPLL6 2
|
||||
#define GPLL4 3
|
||||
#define PCNOC_BFDCD_CLK_SRC 4
|
||||
#define GPLL2 5
|
||||
#define NSS_CRYPTO_PLL 6
|
||||
#define NSS_PPE_CLK_SRC 7
|
||||
#define GCC_XO_CLK_SRC 8
|
||||
#define NSS_CE_CLK_SRC 9
|
||||
#define GCC_SLEEP_CLK_SRC 10
|
||||
#define APSS_AHB_CLK_SRC 11
|
||||
#define NSS_PORT5_RX_CLK_SRC 12
|
||||
#define NSS_PORT5_TX_CLK_SRC 13
|
||||
#define PCIE0_AXI_CLK_SRC 14
|
||||
#define USB0_MASTER_CLK_SRC 15
|
||||
#define APSS_AHB_POSTDIV_CLK_SRC 16
|
||||
#define NSS_PORT1_RX_CLK_SRC 17
|
||||
#define NSS_PORT1_TX_CLK_SRC 18
|
||||
#define NSS_PORT2_RX_CLK_SRC 19
|
||||
#define NSS_PORT2_TX_CLK_SRC 20
|
||||
#define NSS_PORT3_RX_CLK_SRC 21
|
||||
#define NSS_PORT3_TX_CLK_SRC 22
|
||||
#define NSS_PORT4_RX_CLK_SRC 23
|
||||
#define NSS_PORT4_TX_CLK_SRC 24
|
||||
#define NSS_PORT5_RX_DIV_CLK_SRC 25
|
||||
#define NSS_PORT5_TX_DIV_CLK_SRC 26
|
||||
#define APSS_AXI_CLK_SRC 27
|
||||
#define NSS_CRYPTO_CLK_SRC 28
|
||||
#define NSS_PORT1_RX_DIV_CLK_SRC 29
|
||||
#define NSS_PORT1_TX_DIV_CLK_SRC 30
|
||||
#define NSS_PORT2_RX_DIV_CLK_SRC 31
|
||||
#define NSS_PORT2_TX_DIV_CLK_SRC 32
|
||||
#define NSS_PORT3_RX_DIV_CLK_SRC 33
|
||||
#define NSS_PORT3_TX_DIV_CLK_SRC 34
|
||||
#define NSS_PORT4_RX_DIV_CLK_SRC 35
|
||||
#define NSS_PORT4_TX_DIV_CLK_SRC 36
|
||||
#define NSS_UBI0_CLK_SRC 37
|
||||
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38
|
||||
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39
|
||||
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40
|
||||
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41
|
||||
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42
|
||||
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43
|
||||
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44
|
||||
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45
|
||||
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46
|
||||
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47
|
||||
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48
|
||||
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49
|
||||
#define BLSP1_UART1_APPS_CLK_SRC 50
|
||||
#define BLSP1_UART2_APPS_CLK_SRC 51
|
||||
#define BLSP1_UART3_APPS_CLK_SRC 52
|
||||
#define BLSP1_UART4_APPS_CLK_SRC 53
|
||||
#define BLSP1_UART5_APPS_CLK_SRC 54
|
||||
#define BLSP1_UART6_APPS_CLK_SRC 55
|
||||
#define CRYPTO_CLK_SRC 56
|
||||
#define NSS_UBI0_DIV_CLK_SRC 57
|
||||
#define PCIE0_AUX_CLK_SRC 58
|
||||
#define PCIE0_PIPE_CLK_SRC 59
|
||||
#define SDCC1_APPS_CLK_SRC 60
|
||||
#define USB0_AUX_CLK_SRC 61
|
||||
#define USB0_MOCK_UTMI_CLK_SRC 62
|
||||
#define USB0_PIPE_CLK_SRC 63
|
||||
#define USB1_MOCK_UTMI_CLK_SRC 64
|
||||
#define GCC_APSS_AHB_CLK 65
|
||||
#define GCC_APSS_AXI_CLK 66
|
||||
#define GCC_BLSP1_AHB_CLK 67
|
||||
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68
|
||||
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69
|
||||
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70
|
||||
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71
|
||||
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72
|
||||
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73
|
||||
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74
|
||||
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75
|
||||
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76
|
||||
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77
|
||||
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78
|
||||
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79
|
||||
#define GCC_BLSP1_UART1_APPS_CLK 80
|
||||
#define GCC_BLSP1_UART2_APPS_CLK 81
|
||||
#define GCC_BLSP1_UART3_APPS_CLK 82
|
||||
#define GCC_BLSP1_UART4_APPS_CLK 83
|
||||
#define GCC_BLSP1_UART5_APPS_CLK 84
|
||||
#define GCC_BLSP1_UART6_APPS_CLK 85
|
||||
#define GCC_CRYPTO_AHB_CLK 86
|
||||
#define GCC_CRYPTO_AXI_CLK 87
|
||||
#define GCC_CRYPTO_CLK 88
|
||||
#define GCC_XO_CLK 89
|
||||
#define GCC_XO_DIV4_CLK 90
|
||||
#define GCC_MDIO_AHB_CLK 91
|
||||
#define GCC_CRYPTO_PPE_CLK 92
|
||||
#define GCC_NSS_CE_APB_CLK 93
|
||||
#define GCC_NSS_CE_AXI_CLK 94
|
||||
#define GCC_NSS_CFG_CLK 95
|
||||
#define GCC_NSS_CRYPTO_CLK 96
|
||||
#define GCC_NSS_CSR_CLK 97
|
||||
#define GCC_NSS_EDMA_CFG_CLK 98
|
||||
#define GCC_NSS_EDMA_CLK 99
|
||||
#define GCC_NSS_NOC_CLK 100
|
||||
#define GCC_NSS_PORT1_RX_CLK 101
|
||||
#define GCC_NSS_PORT1_TX_CLK 102
|
||||
#define GCC_NSS_PORT2_RX_CLK 103
|
||||
#define GCC_NSS_PORT2_TX_CLK 104
|
||||
#define GCC_NSS_PORT3_RX_CLK 105
|
||||
#define GCC_NSS_PORT3_TX_CLK 106
|
||||
#define GCC_NSS_PORT4_RX_CLK 107
|
||||
#define GCC_NSS_PORT4_TX_CLK 108
|
||||
#define GCC_NSS_PORT5_RX_CLK 109
|
||||
#define GCC_NSS_PORT5_TX_CLK 110
|
||||
#define GCC_NSS_PPE_CFG_CLK 111
|
||||
#define GCC_NSS_PPE_CLK 112
|
||||
#define GCC_NSS_PPE_IPE_CLK 113
|
||||
#define GCC_NSS_PTP_REF_CLK 114
|
||||
#define GCC_NSSNOC_CE_APB_CLK 115
|
||||
#define GCC_NSSNOC_CE_AXI_CLK 116
|
||||
#define GCC_NSSNOC_CRYPTO_CLK 117
|
||||
#define GCC_NSSNOC_PPE_CFG_CLK 118
|
||||
#define GCC_NSSNOC_PPE_CLK 119
|
||||
#define GCC_NSSNOC_QOSGEN_REF_CLK 120
|
||||
#define GCC_NSSNOC_TIMEOUT_REF_CLK 121
|
||||
#define GCC_NSSNOC_UBI0_AHB_CLK 122
|
||||
#define GCC_PORT1_MAC_CLK 123
|
||||
#define GCC_PORT2_MAC_CLK 124
|
||||
#define GCC_PORT3_MAC_CLK 125
|
||||
#define GCC_PORT4_MAC_CLK 126
|
||||
#define GCC_PORT5_MAC_CLK 127
|
||||
#define GCC_UBI0_AHB_CLK 128
|
||||
#define GCC_UBI0_AXI_CLK 129
|
||||
#define GCC_UBI0_CORE_CLK 130
|
||||
#define GCC_PCIE0_AHB_CLK 131
|
||||
#define GCC_PCIE0_AUX_CLK 132
|
||||
#define GCC_PCIE0_AXI_M_CLK 133
|
||||
#define GCC_PCIE0_AXI_S_CLK 134
|
||||
#define GCC_PCIE0_PIPE_CLK 135
|
||||
#define GCC_PRNG_AHB_CLK 136
|
||||
#define GCC_QPIC_AHB_CLK 137
|
||||
#define GCC_QPIC_CLK 138
|
||||
#define GCC_SDCC1_AHB_CLK 139
|
||||
#define GCC_SDCC1_APPS_CLK 140
|
||||
#define GCC_UNIPHY0_AHB_CLK 141
|
||||
#define GCC_UNIPHY0_PORT1_RX_CLK 142
|
||||
#define GCC_UNIPHY0_PORT1_TX_CLK 143
|
||||
#define GCC_UNIPHY0_PORT2_RX_CLK 144
|
||||
#define GCC_UNIPHY0_PORT2_TX_CLK 145
|
||||
#define GCC_UNIPHY0_PORT3_RX_CLK 146
|
||||
#define GCC_UNIPHY0_PORT3_TX_CLK 147
|
||||
#define GCC_UNIPHY0_PORT4_RX_CLK 148
|
||||
#define GCC_UNIPHY0_PORT4_TX_CLK 149
|
||||
#define GCC_UNIPHY0_PORT5_RX_CLK 150
|
||||
#define GCC_UNIPHY0_PORT5_TX_CLK 151
|
||||
#define GCC_UNIPHY0_SYS_CLK 152
|
||||
#define GCC_UNIPHY1_AHB_CLK 153
|
||||
#define GCC_UNIPHY1_PORT5_RX_CLK 154
|
||||
#define GCC_UNIPHY1_PORT5_TX_CLK 155
|
||||
#define GCC_UNIPHY1_SYS_CLK 156
|
||||
#define GCC_USB0_AUX_CLK 157
|
||||
#define GCC_USB0_MASTER_CLK 158
|
||||
#define GCC_USB0_MOCK_UTMI_CLK 159
|
||||
#define GCC_USB0_PHY_CFG_AHB_CLK 160
|
||||
#define GCC_USB0_PIPE_CLK 161
|
||||
#define GCC_USB0_SLEEP_CLK 162
|
||||
#define GCC_USB1_MASTER_CLK 163
|
||||
#define GCC_USB1_MOCK_UTMI_CLK 164
|
||||
#define GCC_USB1_PHY_CFG_AHB_CLK 165
|
||||
#define GCC_USB1_SLEEP_CLK 166
|
||||
#define GP1_CLK_SRC 167
|
||||
#define GP2_CLK_SRC 168
|
||||
#define GP3_CLK_SRC 169
|
||||
#define GCC_GP1_CLK 170
|
||||
#define GCC_GP2_CLK 171
|
||||
#define GCC_GP3_CLK 172
|
||||
#define SYSTEM_NOC_BFDCD_CLK_SRC 173
|
||||
#define GCC_NSSNOC_SNOC_CLK 174
|
||||
#define GCC_UBI0_NC_AXI_CLK 175
|
||||
#define GCC_UBI1_NC_AXI_CLK 176
|
||||
#define GPLL0_MAIN 177
|
||||
#define UBI32_PLL_MAIN 178
|
||||
#define GPLL6_MAIN 179
|
||||
#define GPLL4_MAIN 180
|
||||
#define GPLL2_MAIN 181
|
||||
#define NSS_CRYPTO_PLL_MAIN 182
|
||||
#define GCC_CMN_12GPLL_AHB_CLK 183
|
||||
#define GCC_CMN_12GPLL_SYS_CLK 184
|
||||
#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185
|
||||
#define GCC_SYS_NOC_USB0_AXI_CLK 186
|
||||
#define GCC_SYS_NOC_PCIE0_AXI_CLK 187
|
||||
#define QDSS_TSCTR_CLK_SRC 188
|
||||
#define QDSS_AT_CLK_SRC 189
|
||||
#define GCC_QDSS_AT_CLK 190
|
||||
#define GCC_QDSS_DAP_CLK 191
|
||||
#define ADSS_PWM_CLK_SRC 192
|
||||
#define GCC_ADSS_PWM_CLK 193
|
||||
#define SDCC1_ICE_CORE_CLK_SRC 194
|
||||
#define GCC_SDCC1_ICE_CORE_CLK 195
|
||||
#define GCC_DCC_CLK 196
|
||||
#define PCIE0_RCHNG_CLK_SRC 197
|
||||
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198
|
||||
#define PCIE0_RCHNG_CLK 199
|
||||
#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200
|
||||
#define WCSS_AHB_CLK_SRC 201
|
||||
#define Q6_AXI_CLK_SRC 202
|
||||
#define GCC_Q6SS_PCLKDBG_CLK 203
|
||||
#define GCC_Q6_TSCTR_1TO2_CLK 204
|
||||
#define GCC_WCSS_CORE_TBU_CLK 205
|
||||
#define GCC_WCSS_AXI_M_CLK 206
|
||||
#define GCC_SYS_NOC_WCSS_AHB_CLK 207
|
||||
#define GCC_Q6_AXIM_CLK 208
|
||||
#define GCC_Q6SS_ATBM_CLK 209
|
||||
#define GCC_WCSS_Q6_TBU_CLK 210
|
||||
#define GCC_Q6_AXIM2_CLK 211
|
||||
#define GCC_Q6_AHB_CLK 212
|
||||
#define GCC_Q6_AHB_S_CLK 213
|
||||
#define GCC_WCSS_DBG_IFC_APB_CLK 214
|
||||
#define GCC_WCSS_DBG_IFC_ATB_CLK 215
|
||||
#define GCC_WCSS_DBG_IFC_NTS_CLK 216
|
||||
#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217
|
||||
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218
|
||||
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219
|
||||
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220
|
||||
#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221
|
||||
#define GCC_WCSS_ECAHB_CLK 222
|
||||
#define GCC_WCSS_ACMT_CLK 223
|
||||
#define GCC_WCSS_AHB_S_CLK 224
|
||||
#define GCC_RBCPR_WCSS_CLK 225
|
||||
#define RBCPR_WCSS_CLK_SRC 226
|
||||
#define GCC_RBCPR_WCSS_AHB_CLK 227
|
||||
#define GCC_LPASS_CORE_AXIM_CLK 228
|
||||
#define GCC_LPASS_SNOC_CFG_CLK 229
|
||||
#define GCC_LPASS_Q6_AXIM_CLK 230
|
||||
#define GCC_LPASS_Q6_ATBM_AT_CLK 231
|
||||
#define GCC_LPASS_Q6_PCLKDBG_CLK 232
|
||||
#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233
|
||||
#define GCC_LPASS_Q6SS_TRIG_CLK 234
|
||||
#define GCC_LPASS_TBU_CLK 235
|
||||
#define LPASS_CORE_AXIM_CLK_SRC 236
|
||||
#define LPASS_SNOC_CFG_CLK_SRC 237
|
||||
#define LPASS_Q6_AXIM_CLK_SRC 238
|
||||
#define GCC_PCNOC_LPASS_CLK 239
|
||||
#define GCC_UBI0_UTCM_CLK 240
|
||||
#define SNOC_NSSNOC_BFDCD_CLK_SRC 241
|
||||
#define GCC_SNOC_NSSNOC_CLK 242
|
||||
#define GCC_MEM_NOC_Q6_AXI_CLK 243
|
||||
#define GCC_MEM_NOC_UBI32_CLK 244
|
||||
#define GCC_MEM_NOC_LPASS_CLK 245
|
||||
#define GCC_SNOC_LPASS_CFG_CLK 246
|
||||
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247
|
||||
#define GCC_QDSS_STM_CLK 248
|
||||
#define GCC_QDSS_TRACECLKIN_CLK 249
|
||||
#define QDSS_STM_CLK_SRC 250
|
||||
#define QDSS_TRACECLKIN_CLK_SRC 251
|
||||
#define GCC_NSSNOC_ATB_CLK 252
|
||||
#endif
|
||||
@@ -182,6 +182,7 @@
|
||||
#define GCC_MSS_GPLL0_DIV_CLK_SRC 173
|
||||
#define GCC_MSS_SNOC_AXI_CLK 174
|
||||
#define GCC_MSS_MNOC_BIMC_AXI_CLK 175
|
||||
#define GCC_BIMC_GFX_CLK 176
|
||||
|
||||
#define PCIE_0_GDSC 0
|
||||
#define UFS_GDSC 1
|
||||
|
||||
21
include/dt-bindings/clock/qcom,gpucc-sc7180.h
Normal file
21
include/dt-bindings/clock/qcom,gpucc-sc7180.h
Normal file
@@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
|
||||
|
||||
#define GPU_CC_PLL1 0
|
||||
#define GPU_CC_AHB_CLK 1
|
||||
#define GPU_CC_CRC_AHB_CLK 2
|
||||
#define GPU_CC_CX_GMU_CLK 3
|
||||
#define GPU_CC_CX_SNOC_DVM_CLK 4
|
||||
#define GPU_CC_CXO_AON_CLK 5
|
||||
#define GPU_CC_CXO_CLK 6
|
||||
#define GPU_CC_GMU_CLK_SRC 7
|
||||
|
||||
/* CAM_CC GDSCRs */
|
||||
#define CX_GDSC 0
|
||||
|
||||
#endif
|
||||
210
include/dt-bindings/clock/qcom,mmcc-msm8998.h
Normal file
210
include/dt-bindings/clock/qcom,mmcc-msm8998.h
Normal file
@@ -0,0 +1,210 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
|
||||
#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
|
||||
|
||||
#define MMPLL0 0
|
||||
#define MMPLL0_OUT_EVEN 1
|
||||
#define MMPLL1 2
|
||||
#define MMPLL1_OUT_EVEN 3
|
||||
#define MMPLL3 4
|
||||
#define MMPLL3_OUT_EVEN 5
|
||||
#define MMPLL4 6
|
||||
#define MMPLL4_OUT_EVEN 7
|
||||
#define MMPLL5 8
|
||||
#define MMPLL5_OUT_EVEN 9
|
||||
#define MMPLL6 10
|
||||
#define MMPLL6_OUT_EVEN 11
|
||||
#define MMPLL7 12
|
||||
#define MMPLL7_OUT_EVEN 13
|
||||
#define MMPLL10 14
|
||||
#define MMPLL10_OUT_EVEN 15
|
||||
#define BYTE0_CLK_SRC 16
|
||||
#define BYTE1_CLK_SRC 17
|
||||
#define CCI_CLK_SRC 18
|
||||
#define CPP_CLK_SRC 19
|
||||
#define CSI0_CLK_SRC 20
|
||||
#define CSI1_CLK_SRC 21
|
||||
#define CSI2_CLK_SRC 22
|
||||
#define CSI3_CLK_SRC 23
|
||||
#define CSIPHY_CLK_SRC 24
|
||||
#define CSI0PHYTIMER_CLK_SRC 25
|
||||
#define CSI1PHYTIMER_CLK_SRC 26
|
||||
#define CSI2PHYTIMER_CLK_SRC 27
|
||||
#define DP_AUX_CLK_SRC 28
|
||||
#define DP_CRYPTO_CLK_SRC 29
|
||||
#define DP_LINK_CLK_SRC 30
|
||||
#define DP_PIXEL_CLK_SRC 31
|
||||
#define ESC0_CLK_SRC 32
|
||||
#define ESC1_CLK_SRC 33
|
||||
#define EXTPCLK_CLK_SRC 34
|
||||
#define FD_CORE_CLK_SRC 35
|
||||
#define HDMI_CLK_SRC 36
|
||||
#define JPEG0_CLK_SRC 37
|
||||
#define MAXI_CLK_SRC 38
|
||||
#define MCLK0_CLK_SRC 39
|
||||
#define MCLK1_CLK_SRC 40
|
||||
#define MCLK2_CLK_SRC 41
|
||||
#define MCLK3_CLK_SRC 42
|
||||
#define MDP_CLK_SRC 43
|
||||
#define VSYNC_CLK_SRC 44
|
||||
#define AHB_CLK_SRC 45
|
||||
#define AXI_CLK_SRC 46
|
||||
#define PCLK0_CLK_SRC 47
|
||||
#define PCLK1_CLK_SRC 48
|
||||
#define ROT_CLK_SRC 49
|
||||
#define VIDEO_CORE_CLK_SRC 50
|
||||
#define VIDEO_SUBCORE0_CLK_SRC 51
|
||||
#define VIDEO_SUBCORE1_CLK_SRC 52
|
||||
#define VFE0_CLK_SRC 53
|
||||
#define VFE1_CLK_SRC 54
|
||||
#define MISC_AHB_CLK 55
|
||||
#define VIDEO_CORE_CLK 56
|
||||
#define VIDEO_AHB_CLK 57
|
||||
#define VIDEO_AXI_CLK 58
|
||||
#define VIDEO_MAXI_CLK 59
|
||||
#define VIDEO_SUBCORE0_CLK 60
|
||||
#define VIDEO_SUBCORE1_CLK 61
|
||||
#define MDSS_AHB_CLK 62
|
||||
#define MDSS_HDMI_DP_AHB_CLK 63
|
||||
#define MDSS_AXI_CLK 64
|
||||
#define MDSS_PCLK0_CLK 65
|
||||
#define MDSS_PCLK1_CLK 66
|
||||
#define MDSS_MDP_CLK 67
|
||||
#define MDSS_MDP_LUT_CLK 68
|
||||
#define MDSS_EXTPCLK_CLK 69
|
||||
#define MDSS_VSYNC_CLK 70
|
||||
#define MDSS_HDMI_CLK 71
|
||||
#define MDSS_BYTE0_CLK 72
|
||||
#define MDSS_BYTE1_CLK 73
|
||||
#define MDSS_ESC0_CLK 74
|
||||
#define MDSS_ESC1_CLK 75
|
||||
#define MDSS_ROT_CLK 76
|
||||
#define MDSS_DP_LINK_CLK 77
|
||||
#define MDSS_DP_LINK_INTF_CLK 78
|
||||
#define MDSS_DP_CRYPTO_CLK 79
|
||||
#define MDSS_DP_PIXEL_CLK 80
|
||||
#define MDSS_DP_AUX_CLK 81
|
||||
#define MDSS_BYTE0_INTF_CLK 82
|
||||
#define MDSS_BYTE1_INTF_CLK 83
|
||||
#define CAMSS_CSI0PHYTIMER_CLK 84
|
||||
#define CAMSS_CSI1PHYTIMER_CLK 85
|
||||
#define CAMSS_CSI2PHYTIMER_CLK 86
|
||||
#define CAMSS_CSI0_CLK 87
|
||||
#define CAMSS_CSI0_AHB_CLK 88
|
||||
#define CAMSS_CSI0RDI_CLK 89
|
||||
#define CAMSS_CSI0PIX_CLK 90
|
||||
#define CAMSS_CSI1_CLK 91
|
||||
#define CAMSS_CSI1_AHB_CLK 92
|
||||
#define CAMSS_CSI1RDI_CLK 93
|
||||
#define CAMSS_CSI1PIX_CLK 94
|
||||
#define CAMSS_CSI2_CLK 95
|
||||
#define CAMSS_CSI2_AHB_CLK 96
|
||||
#define CAMSS_CSI2RDI_CLK 97
|
||||
#define CAMSS_CSI2PIX_CLK 98
|
||||
#define CAMSS_CSI3_CLK 99
|
||||
#define CAMSS_CSI3_AHB_CLK 100
|
||||
#define CAMSS_CSI3RDI_CLK 101
|
||||
#define CAMSS_CSI3PIX_CLK 102
|
||||
#define CAMSS_ISPIF_AHB_CLK 103
|
||||
#define CAMSS_CCI_CLK 104
|
||||
#define CAMSS_CCI_AHB_CLK 105
|
||||
#define CAMSS_MCLK0_CLK 106
|
||||
#define CAMSS_MCLK1_CLK 107
|
||||
#define CAMSS_MCLK2_CLK 108
|
||||
#define CAMSS_MCLK3_CLK 109
|
||||
#define CAMSS_TOP_AHB_CLK 110
|
||||
#define CAMSS_AHB_CLK 111
|
||||
#define CAMSS_MICRO_AHB_CLK 112
|
||||
#define CAMSS_JPEG0_CLK 113
|
||||
#define CAMSS_JPEG_AHB_CLK 114
|
||||
#define CAMSS_JPEG_AXI_CLK 115
|
||||
#define CAMSS_VFE0_AHB_CLK 116
|
||||
#define CAMSS_VFE1_AHB_CLK 117
|
||||
#define CAMSS_VFE0_CLK 118
|
||||
#define CAMSS_VFE1_CLK 119
|
||||
#define CAMSS_CPP_CLK 120
|
||||
#define CAMSS_CPP_AHB_CLK 121
|
||||
#define CAMSS_VFE_VBIF_AHB_CLK 122
|
||||
#define CAMSS_VFE_VBIF_AXI_CLK 123
|
||||
#define CAMSS_CPP_AXI_CLK 124
|
||||
#define CAMSS_CPP_VBIF_AHB_CLK 125
|
||||
#define CAMSS_CSI_VFE0_CLK 126
|
||||
#define CAMSS_CSI_VFE1_CLK 127
|
||||
#define CAMSS_VFE0_STREAM_CLK 128
|
||||
#define CAMSS_VFE1_STREAM_CLK 129
|
||||
#define CAMSS_CPHY_CSID0_CLK 130
|
||||
#define CAMSS_CPHY_CSID1_CLK 131
|
||||
#define CAMSS_CPHY_CSID2_CLK 132
|
||||
#define CAMSS_CPHY_CSID3_CLK 133
|
||||
#define CAMSS_CSIPHY0_CLK 134
|
||||
#define CAMSS_CSIPHY1_CLK 135
|
||||
#define CAMSS_CSIPHY2_CLK 136
|
||||
#define FD_CORE_CLK 137
|
||||
#define FD_CORE_UAR_CLK 138
|
||||
#define FD_AHB_CLK 139
|
||||
#define MNOC_AHB_CLK 140
|
||||
#define BIMC_SMMU_AHB_CLK 141
|
||||
#define BIMC_SMMU_AXI_CLK 142
|
||||
#define MNOC_MAXI_CLK 143
|
||||
#define VMEM_MAXI_CLK 144
|
||||
#define VMEM_AHB_CLK 145
|
||||
|
||||
#define SPDM_BCR 0
|
||||
#define SPDM_RM_BCR 1
|
||||
#define MISC_BCR 2
|
||||
#define VIDEO_TOP_BCR 3
|
||||
#define THROTTLE_VIDEO_BCR 4
|
||||
#define MDSS_BCR 5
|
||||
#define THROTTLE_MDSS_BCR 6
|
||||
#define CAMSS_PHY0_BCR 7
|
||||
#define CAMSS_PHY1_BCR 8
|
||||
#define CAMSS_PHY2_BCR 9
|
||||
#define CAMSS_CSI0_BCR 10
|
||||
#define CAMSS_CSI0RDI_BCR 11
|
||||
#define CAMSS_CSI0PIX_BCR 12
|
||||
#define CAMSS_CSI1_BCR 13
|
||||
#define CAMSS_CSI1RDI_BCR 14
|
||||
#define CAMSS_CSI1PIX_BCR 15
|
||||
#define CAMSS_CSI2_BCR 16
|
||||
#define CAMSS_CSI2RDI_BCR 17
|
||||
#define CAMSS_CSI2PIX_BCR 18
|
||||
#define CAMSS_CSI3_BCR 19
|
||||
#define CAMSS_CSI3RDI_BCR 20
|
||||
#define CAMSS_CSI3PIX_BCR 21
|
||||
#define CAMSS_ISPIF_BCR 22
|
||||
#define CAMSS_CCI_BCR 23
|
||||
#define CAMSS_TOP_BCR 24
|
||||
#define CAMSS_AHB_BCR 25
|
||||
#define CAMSS_MICRO_BCR 26
|
||||
#define CAMSS_JPEG_BCR 27
|
||||
#define CAMSS_VFE0_BCR 28
|
||||
#define CAMSS_VFE1_BCR 29
|
||||
#define CAMSS_VFE_VBIF_BCR 30
|
||||
#define CAMSS_CPP_TOP_BCR 31
|
||||
#define CAMSS_CPP_BCR 32
|
||||
#define CAMSS_CSI_VFE0_BCR 33
|
||||
#define CAMSS_CSI_VFE1_BCR 34
|
||||
#define CAMSS_FD_BCR 35
|
||||
#define THROTTLE_CAMSS_BCR 36
|
||||
#define MNOCAHB_BCR 37
|
||||
#define MNOCAXI_BCR 38
|
||||
#define BMIC_SMMU_BCR 39
|
||||
#define MNOC_MAXI_BCR 40
|
||||
#define VMEM_BCR 41
|
||||
#define BTO_BCR 42
|
||||
|
||||
#define VIDEO_TOP_GDSC 1
|
||||
#define VIDEO_SUBCORE0_GDSC 2
|
||||
#define VIDEO_SUBCORE1_GDSC 3
|
||||
#define MDSS_GDSC 4
|
||||
#define CAMSS_TOP_GDSC 5
|
||||
#define CAMSS_VFE0_GDSC 6
|
||||
#define CAMSS_VFE1_GDSC 7
|
||||
#define CAMSS_CPP_GDSC 8
|
||||
#define BIMC_SMMU_GDSC 9
|
||||
|
||||
#endif
|
||||
23
include/dt-bindings/clock/qcom,videocc-sc7180.h
Normal file
23
include/dt-bindings/clock/qcom,videocc-sc7180.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
|
||||
|
||||
/* VIDEO_CC clocks */
|
||||
#define VIDEO_PLL0 0
|
||||
#define VIDEO_CC_VCODEC0_AXI_CLK 1
|
||||
#define VIDEO_CC_VCODEC0_CORE_CLK 2
|
||||
#define VIDEO_CC_VENUS_AHB_CLK 3
|
||||
#define VIDEO_CC_VENUS_CLK_SRC 4
|
||||
#define VIDEO_CC_VENUS_CTL_AXI_CLK 5
|
||||
#define VIDEO_CC_VENUS_CTL_CORE_CLK 6
|
||||
#define VIDEO_CC_XO_CLK 7
|
||||
|
||||
/* VIDEO_CC GDSCRs */
|
||||
#define VENUS_GDSC 0
|
||||
#define VCODEC0_GDSC 1
|
||||
|
||||
#endif
|
||||
123
include/dt-bindings/clock/xlnx-versal-clk.h
Normal file
123
include/dt-bindings/clock/xlnx-versal-clk.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 Xilinx Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_VERSAL_H
|
||||
#define _DT_BINDINGS_CLK_VERSAL_H
|
||||
|
||||
#define PMC_PLL 1
|
||||
#define APU_PLL 2
|
||||
#define RPU_PLL 3
|
||||
#define CPM_PLL 4
|
||||
#define NOC_PLL 5
|
||||
#define PLL_MAX 6
|
||||
#define PMC_PRESRC 7
|
||||
#define PMC_POSTCLK 8
|
||||
#define PMC_PLL_OUT 9
|
||||
#define PPLL 10
|
||||
#define NOC_PRESRC 11
|
||||
#define NOC_POSTCLK 12
|
||||
#define NOC_PLL_OUT 13
|
||||
#define NPLL 14
|
||||
#define APU_PRESRC 15
|
||||
#define APU_POSTCLK 16
|
||||
#define APU_PLL_OUT 17
|
||||
#define APLL 18
|
||||
#define RPU_PRESRC 19
|
||||
#define RPU_POSTCLK 20
|
||||
#define RPU_PLL_OUT 21
|
||||
#define RPLL 22
|
||||
#define CPM_PRESRC 23
|
||||
#define CPM_POSTCLK 24
|
||||
#define CPM_PLL_OUT 25
|
||||
#define CPLL 26
|
||||
#define PPLL_TO_XPD 27
|
||||
#define NPLL_TO_XPD 28
|
||||
#define APLL_TO_XPD 29
|
||||
#define RPLL_TO_XPD 30
|
||||
#define EFUSE_REF 31
|
||||
#define SYSMON_REF 32
|
||||
#define IRO_SUSPEND_REF 33
|
||||
#define USB_SUSPEND 34
|
||||
#define SWITCH_TIMEOUT 35
|
||||
#define RCLK_PMC 36
|
||||
#define RCLK_LPD 37
|
||||
#define WDT 38
|
||||
#define TTC0 39
|
||||
#define TTC1 40
|
||||
#define TTC2 41
|
||||
#define TTC3 42
|
||||
#define GEM_TSU 43
|
||||
#define GEM_TSU_LB 44
|
||||
#define MUXED_IRO_DIV2 45
|
||||
#define MUXED_IRO_DIV4 46
|
||||
#define PSM_REF 47
|
||||
#define GEM0_RX 48
|
||||
#define GEM0_TX 49
|
||||
#define GEM1_RX 50
|
||||
#define GEM1_TX 51
|
||||
#define CPM_CORE_REF 52
|
||||
#define CPM_LSBUS_REF 53
|
||||
#define CPM_DBG_REF 54
|
||||
#define CPM_AUX0_REF 55
|
||||
#define CPM_AUX1_REF 56
|
||||
#define QSPI_REF 57
|
||||
#define OSPI_REF 58
|
||||
#define SDIO0_REF 59
|
||||
#define SDIO1_REF 60
|
||||
#define PMC_LSBUS_REF 61
|
||||
#define I2C_REF 62
|
||||
#define TEST_PATTERN_REF 63
|
||||
#define DFT_OSC_REF 64
|
||||
#define PMC_PL0_REF 65
|
||||
#define PMC_PL1_REF 66
|
||||
#define PMC_PL2_REF 67
|
||||
#define PMC_PL3_REF 68
|
||||
#define CFU_REF 69
|
||||
#define SPARE_REF 70
|
||||
#define NPI_REF 71
|
||||
#define HSM0_REF 72
|
||||
#define HSM1_REF 73
|
||||
#define SD_DLL_REF 74
|
||||
#define FPD_TOP_SWITCH 75
|
||||
#define FPD_LSBUS 76
|
||||
#define ACPU 77
|
||||
#define DBG_TRACE 78
|
||||
#define DBG_FPD 79
|
||||
#define LPD_TOP_SWITCH 80
|
||||
#define ADMA 81
|
||||
#define LPD_LSBUS 82
|
||||
#define CPU_R5 83
|
||||
#define CPU_R5_CORE 84
|
||||
#define CPU_R5_OCM 85
|
||||
#define CPU_R5_OCM2 86
|
||||
#define IOU_SWITCH 87
|
||||
#define GEM0_REF 88
|
||||
#define GEM1_REF 89
|
||||
#define GEM_TSU_REF 90
|
||||
#define USB0_BUS_REF 91
|
||||
#define UART0_REF 92
|
||||
#define UART1_REF 93
|
||||
#define SPI0_REF 94
|
||||
#define SPI1_REF 95
|
||||
#define CAN0_REF 96
|
||||
#define CAN1_REF 97
|
||||
#define I2C0_REF 98
|
||||
#define I2C1_REF 99
|
||||
#define DBG_LPD 100
|
||||
#define TIMESTAMP_REF 101
|
||||
#define DBG_TSTMP 102
|
||||
#define CPM_TOPSW_REF 103
|
||||
#define USB3_DUAL_REF 104
|
||||
#define OUTCLK_MAX 105
|
||||
#define REF_CLK 106
|
||||
#define PL_ALT_REF_CLK 107
|
||||
#define MUXED_IRO 108
|
||||
#define PL_EXT 109
|
||||
#define PL_LB 110
|
||||
#define MIO_50_OR_51 111
|
||||
#define MIO_24_OR_25 112
|
||||
|
||||
#endif
|
||||
157
include/dt-bindings/reset/qcom,gcc-ipq6018.h
Normal file
157
include/dt-bindings/reset/qcom,gcc-ipq6018.h
Normal file
@@ -0,0 +1,157 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H
|
||||
#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H
|
||||
|
||||
#define GCC_BLSP1_BCR 0
|
||||
#define GCC_BLSP1_QUP1_BCR 1
|
||||
#define GCC_BLSP1_UART1_BCR 2
|
||||
#define GCC_BLSP1_QUP2_BCR 3
|
||||
#define GCC_BLSP1_UART2_BCR 4
|
||||
#define GCC_BLSP1_QUP3_BCR 5
|
||||
#define GCC_BLSP1_UART3_BCR 6
|
||||
#define GCC_BLSP1_QUP4_BCR 7
|
||||
#define GCC_BLSP1_UART4_BCR 8
|
||||
#define GCC_BLSP1_QUP5_BCR 9
|
||||
#define GCC_BLSP1_UART5_BCR 10
|
||||
#define GCC_BLSP1_QUP6_BCR 11
|
||||
#define GCC_BLSP1_UART6_BCR 12
|
||||
#define GCC_IMEM_BCR 13
|
||||
#define GCC_SMMU_BCR 14
|
||||
#define GCC_APSS_TCU_BCR 15
|
||||
#define GCC_SMMU_XPU_BCR 16
|
||||
#define GCC_PCNOC_TBU_BCR 17
|
||||
#define GCC_SMMU_CFG_BCR 18
|
||||
#define GCC_PRNG_BCR 19
|
||||
#define GCC_BOOT_ROM_BCR 20
|
||||
#define GCC_CRYPTO_BCR 21
|
||||
#define GCC_WCSS_BCR 22
|
||||
#define GCC_WCSS_Q6_BCR 23
|
||||
#define GCC_NSS_BCR 24
|
||||
#define GCC_SEC_CTRL_BCR 25
|
||||
#define GCC_DDRSS_BCR 26
|
||||
#define GCC_SYSTEM_NOC_BCR 27
|
||||
#define GCC_PCNOC_BCR 28
|
||||
#define GCC_TCSR_BCR 29
|
||||
#define GCC_QDSS_BCR 30
|
||||
#define GCC_DCD_BCR 31
|
||||
#define GCC_MSG_RAM_BCR 32
|
||||
#define GCC_MPM_BCR 33
|
||||
#define GCC_SPDM_BCR 34
|
||||
#define GCC_RBCPR_BCR 35
|
||||
#define GCC_RBCPR_MX_BCR 36
|
||||
#define GCC_TLMM_BCR 37
|
||||
#define GCC_RBCPR_WCSS_BCR 38
|
||||
#define GCC_USB0_PHY_BCR 39
|
||||
#define GCC_USB3PHY_0_PHY_BCR 40
|
||||
#define GCC_USB0_BCR 41
|
||||
#define GCC_USB1_BCR 42
|
||||
#define GCC_QUSB2_0_PHY_BCR 43
|
||||
#define GCC_QUSB2_1_PHY_BCR 44
|
||||
#define GCC_SDCC1_BCR 45
|
||||
#define GCC_SNOC_BUS_TIMEOUT0_BCR 46
|
||||
#define GCC_SNOC_BUS_TIMEOUT1_BCR 47
|
||||
#define GCC_SNOC_BUS_TIMEOUT2_BCR 48
|
||||
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49
|
||||
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50
|
||||
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51
|
||||
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52
|
||||
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53
|
||||
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54
|
||||
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55
|
||||
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56
|
||||
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57
|
||||
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58
|
||||
#define GCC_UNIPHY0_BCR 59
|
||||
#define GCC_UNIPHY1_BCR 60
|
||||
#define GCC_CMN_12GPLL_BCR 61
|
||||
#define GCC_QPIC_BCR 62
|
||||
#define GCC_MDIO_BCR 63
|
||||
#define GCC_WCSS_CORE_TBU_BCR 64
|
||||
#define GCC_WCSS_Q6_TBU_BCR 65
|
||||
#define GCC_USB0_TBU_BCR 66
|
||||
#define GCC_PCIE0_TBU_BCR 67
|
||||
#define GCC_PCIE0_BCR 68
|
||||
#define GCC_PCIE0_PHY_BCR 69
|
||||
#define GCC_PCIE0PHY_PHY_BCR 70
|
||||
#define GCC_PCIE0_LINK_DOWN_BCR 71
|
||||
#define GCC_DCC_BCR 72
|
||||
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73
|
||||
#define GCC_SMMU_CATS_BCR 74
|
||||
#define GCC_UBI0_AXI_ARES 75
|
||||
#define GCC_UBI0_AHB_ARES 76
|
||||
#define GCC_UBI0_NC_AXI_ARES 77
|
||||
#define GCC_UBI0_DBG_ARES 78
|
||||
#define GCC_UBI0_CORE_CLAMP_ENABLE 79
|
||||
#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80
|
||||
#define GCC_UBI0_UTCM_ARES 81
|
||||
#define GCC_NSS_CFG_ARES 82
|
||||
#define GCC_NSS_NOC_ARES 83
|
||||
#define GCC_NSS_CRYPTO_ARES 84
|
||||
#define GCC_NSS_CSR_ARES 85
|
||||
#define GCC_NSS_CE_APB_ARES 86
|
||||
#define GCC_NSS_CE_AXI_ARES 87
|
||||
#define GCC_NSSNOC_CE_APB_ARES 88
|
||||
#define GCC_NSSNOC_CE_AXI_ARES 89
|
||||
#define GCC_NSSNOC_UBI0_AHB_ARES 90
|
||||
#define GCC_NSSNOC_SNOC_ARES 91
|
||||
#define GCC_NSSNOC_CRYPTO_ARES 92
|
||||
#define GCC_NSSNOC_ATB_ARES 93
|
||||
#define GCC_NSSNOC_QOSGEN_REF_ARES 94
|
||||
#define GCC_NSSNOC_TIMEOUT_REF_ARES 95
|
||||
#define GCC_PCIE0_PIPE_ARES 96
|
||||
#define GCC_PCIE0_SLEEP_ARES 97
|
||||
#define GCC_PCIE0_CORE_STICKY_ARES 98
|
||||
#define GCC_PCIE0_AXI_MASTER_ARES 99
|
||||
#define GCC_PCIE0_AXI_SLAVE_ARES 100
|
||||
#define GCC_PCIE0_AHB_ARES 101
|
||||
#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102
|
||||
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103
|
||||
#define GCC_PPE_FULL_RESET 104
|
||||
#define GCC_UNIPHY0_SOFT_RESET 105
|
||||
#define GCC_UNIPHY0_XPCS_RESET 106
|
||||
#define GCC_UNIPHY1_SOFT_RESET 107
|
||||
#define GCC_UNIPHY1_XPCS_RESET 108
|
||||
#define GCC_EDMA_HW_RESET 109
|
||||
#define GCC_ADSS_BCR 110
|
||||
#define GCC_NSS_NOC_TBU_BCR 111
|
||||
#define GCC_NSSPORT1_RESET 112
|
||||
#define GCC_NSSPORT2_RESET 113
|
||||
#define GCC_NSSPORT3_RESET 114
|
||||
#define GCC_NSSPORT4_RESET 115
|
||||
#define GCC_NSSPORT5_RESET 116
|
||||
#define GCC_UNIPHY0_PORT1_ARES 117
|
||||
#define GCC_UNIPHY0_PORT2_ARES 118
|
||||
#define GCC_UNIPHY0_PORT3_ARES 119
|
||||
#define GCC_UNIPHY0_PORT4_ARES 120
|
||||
#define GCC_UNIPHY0_PORT5_ARES 121
|
||||
#define GCC_UNIPHY0_PORT_4_5_RESET 122
|
||||
#define GCC_UNIPHY0_PORT_4_RESET 123
|
||||
#define GCC_LPASS_BCR 124
|
||||
#define GCC_UBI32_TBU_BCR 125
|
||||
#define GCC_LPASS_TBU_BCR 126
|
||||
#define GCC_WCSSAON_RESET 127
|
||||
#define GCC_LPASS_Q6_AXIM_ARES 128
|
||||
#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129
|
||||
#define GCC_LPASS_Q6SS_TRIG_ARES 130
|
||||
#define GCC_LPASS_Q6_ATBM_AT_ARES 131
|
||||
#define GCC_LPASS_Q6_PCLKDBG_ARES 132
|
||||
#define GCC_LPASS_CORE_AXIM_ARES 133
|
||||
#define GCC_LPASS_SNOC_CFG_ARES 134
|
||||
#define GCC_WCSS_DBG_ARES 135
|
||||
#define GCC_WCSS_ECAHB_ARES 136
|
||||
#define GCC_WCSS_ACMT_ARES 137
|
||||
#define GCC_WCSS_DBG_BDG_ARES 138
|
||||
#define GCC_WCSS_AHB_S_ARES 139
|
||||
#define GCC_WCSS_AXI_M_ARES 140
|
||||
#define GCC_Q6SS_DBG_ARES 141
|
||||
#define GCC_Q6_AHB_S_ARES 142
|
||||
#define GCC_Q6_AHB_ARES 143
|
||||
#define GCC_Q6_AXIM2_ARES 144
|
||||
#define GCC_Q6_AXIM_ARES 145
|
||||
#define GCC_UBI0_CORE_ARES 146
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user