forked from Minki/linux
pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt
Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220707182314.66610-7-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar
Marc Zyngier
parent
35c37efd12
commit
db2e5f21a4
@ -9,8 +9,10 @@
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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@ -89,6 +91,7 @@
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#define PIN(n) (0x0800 + 0x10 + (n))
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#define IOLH(n) (0x1000 + (n) * 8)
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#define IEN(n) (0x1800 + (n) * 8)
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#define ISEL(n) (0x2c80 + (n) * 8)
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#define PWPR (0x3014)
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#define SD_CH(n) (0x3000 + (n) * 4)
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#define QSPI (0x3008)
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@ -112,6 +115,10 @@
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#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
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#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
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#define RZG2L_TINT_MAX_INTERRUPT 32
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#define RZG2L_TINT_IRQ_START_INDEX 9
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#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
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struct rzg2l_dedicated_configs {
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const char *name;
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u32 config;
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@ -137,6 +144,9 @@ struct rzg2l_pinctrl {
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
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spinlock_t bitmap_lock;
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unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
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spinlock_t lock;
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};
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@ -883,8 +893,14 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
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static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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unsigned int virq;
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pinctrl_gpio_free(chip->base + offset);
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virq = irq_find_mapping(chip->irq.domain, offset);
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if (virq)
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irq_dispose_mapping(virq);
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/*
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* Set the GPIO as an input to ensure that the next GPIO request won't
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* drive the GPIO pin as an output.
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@ -1104,14 +1120,221 @@ static struct {
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}
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};
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static int rzg2l_gpio_get_gpioint(unsigned int virq)
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{
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unsigned int gpioint;
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unsigned int i;
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u32 port, bit;
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port = virq / 8;
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bit = virq % 8;
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if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
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bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
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return -EINVAL;
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gpioint = bit;
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for (i = 0; i < port; i++)
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gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
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return gpioint;
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}
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static void rzg2l_gpio_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
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unsigned int hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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void __iomem *addr;
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u32 port;
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u8 bit;
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port = RZG2L_PIN_ID_TO_PORT(hwirq);
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bit = RZG2L_PIN_ID_TO_PIN(hwirq);
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addr = pctrl->base + ISEL(port);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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writel(readl(addr) & ~BIT(bit * 8), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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gpiochip_disable_irq(gc, hwirq);
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irq_chip_disable_parent(d);
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}
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static void rzg2l_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
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unsigned int hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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void __iomem *addr;
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u32 port;
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u8 bit;
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gpiochip_enable_irq(gc, hwirq);
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port = RZG2L_PIN_ID_TO_PORT(hwirq);
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bit = RZG2L_PIN_ID_TO_PIN(hwirq);
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addr = pctrl->base + ISEL(port);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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writel(readl(addr) | BIT(bit * 8), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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irq_chip_enable_parent(d);
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}
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static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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return irq_chip_set_type_parent(d, type);
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}
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static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
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{
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irq_chip_eoi_parent(d);
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}
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static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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seq_printf(p, dev_name(gc->parent));
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}
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static const struct irq_chip rzg2l_gpio_irqchip = {
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.name = "rzg2l-gpio",
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.irq_disable = rzg2l_gpio_irq_disable,
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.irq_enable = rzg2l_gpio_irq_enable,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_type = rzg2l_gpio_irq_set_type,
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.irq_eoi = rzg2l_gpio_irqc_eoi,
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.irq_print_chip = rzg2l_gpio_irq_print_chip,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
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unsigned long flags;
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int gpioint, irq;
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gpioint = rzg2l_gpio_get_gpioint(child);
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if (gpioint < 0)
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return gpioint;
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spin_lock_irqsave(&pctrl->bitmap_lock, flags);
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irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));
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spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
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if (irq < 0)
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return -ENOSPC;
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pctrl->hwirq[irq] = child;
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irq += RZG2L_TINT_IRQ_START_INDEX;
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/* All these interrupts are level high in the CPU */
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*parent_type = IRQ_TYPE_LEVEL_HIGH;
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*parent = RZG2L_PACK_HWIRQ(gpioint, irq);
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return 0;
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}
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static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
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union gpio_irq_fwspec *gfwspec,
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unsigned int parent_hwirq,
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unsigned int parent_type)
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{
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struct irq_fwspec *fwspec = &gfwspec->fwspec;
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fwspec->fwnode = chip->irq.parent_domain->fwnode;
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fwspec->param_count = 2;
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fwspec->param[0] = parent_hwirq;
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fwspec->param[1] = parent_type;
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return 0;
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}
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static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d;
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d = irq_domain_get_irq_data(domain, virq);
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if (d) {
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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unsigned int i;
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for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
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if (pctrl->hwirq[i] == hwirq) {
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spin_lock_irqsave(&pctrl->bitmap_lock, flags);
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bitmap_release_region(pctrl->tint_slot, i, get_order(1));
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spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
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pctrl->hwirq[i] = 0;
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break;
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}
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}
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}
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
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static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
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struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
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struct gpio_chip *chip = &pctrl->gpio_chip;
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unsigned int offset;
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/* Forbid unused lines to be mapped as IRQs */
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for (offset = 0; offset < chip->ngpio; offset++) {
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u32 port, bit;
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port = offset / 8;
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bit = offset % 8;
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if (port >= ARRAY_SIZE(rzg2l_gpio_configs) ||
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bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
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clear_bit(offset, valid_mask);
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}
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}
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static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
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{
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struct device_node *np = pctrl->dev->of_node;
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struct gpio_chip *chip = &pctrl->gpio_chip;
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const char *name = dev_name(pctrl->dev);
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struct irq_domain *parent_domain;
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struct of_phandle_args of_args;
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struct device_node *parent_np;
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struct gpio_irq_chip *girq;
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int ret;
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parent_np = of_irq_find_parent(np);
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if (!parent_np)
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return -ENXIO;
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parent_domain = irq_find_host(parent_np);
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of_node_put(parent_np);
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if (!parent_domain)
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return -EPROBE_DEFER;
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ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
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if (ret) {
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dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
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@ -1138,6 +1361,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
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chip->base = -1;
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chip->ngpio = of_args.args[2];
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girq = &chip->irq;
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gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
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girq->fwnode = of_node_to_fwnode(np);
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girq->parent_domain = parent_domain;
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girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
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girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
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girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
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girq->init_valid_mask = rzg2l_init_irq_valid_mask;
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pctrl->gpio_range.id = 0;
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pctrl->gpio_range.pin_base = 0;
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pctrl->gpio_range.base = 0;
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@ -1253,6 +1485,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
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}
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spin_lock_init(&pctrl->lock);
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spin_lock_init(&pctrl->bitmap_lock);
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platform_set_drvdata(pdev, pctrl);
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