From a03fa77d85a736d3edef1a0b93100902b6db58c0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Aug 2019 10:22:29 +0200 Subject: [PATCH 1/2] ARM: dts: r8a7779: Use SYSC "always-on" PM Domain for HSCIF Hook up HSCIF serial devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Cfr. commit 751e29bbb64ad091 ("ARM: dts: r8a7779: Use SYSC "always-on" PM Domain"). Fixes: 055d15a88f66b096 ("ARM: dts: r8a7779: Add HSCIF0/1 device nodes") Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Ulrich Hecht --- arch/arm/boot/dts/r8a7779.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 3ff259207527..ebf5b7cfe215 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -296,7 +296,7 @@ <&cpg_clocks R8A7779_CLK_S>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; status = "disabled"; }; @@ -309,7 +309,7 @@ <&cpg_clocks R8A7779_CLK_S>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&cpg_clocks>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; status = "disabled"; }; From 57012813f1ba82412cdcc3665b04d4353b357378 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 7 May 2018 11:16:48 +0200 Subject: [PATCH 2/2] ARM: dts: r8a77470: Add PMU device node Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on RZ/G1C by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: Geert Uytterhoeven Tested-by: Fabrizio Castro Reviewed-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 56cb10b42ed9..51806c7f486a 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -63,6 +63,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock";