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drm/amd/powerplay: avoid out of bounds access on array ps.

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check array index first and then visit the array.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-11-14 16:36:08 +08:00 committed by Alex Deucher
parent 1da2c326e4
commit da7800a88c
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -2984,19 +2984,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
data->highest_mclk = memory_clock;
performance_level = &(ps->performance_levels
[ps->performance_level_count++]);
PP_ASSERT_WITH_CODE(
(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
"Performance levels exceeds SMC limit!",
return -EINVAL);
PP_ASSERT_WITH_CODE(
(ps->performance_level_count <=
(ps->performance_level_count <
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
"Performance levels exceeds Driver limit!",
return -EINVAL);
"Performance levels exceeds Driver limit, Skip!",
return 0);
performance_level = &(ps->performance_levels
[ps->performance_level_count++]);
/* Performance levels are arranged from low to high. */
performance_level->memory_clock = memory_clock;