leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: dts: Update the NSPIRE DTS files for DRM

Browse Source 
The DRM subsystem graphics drivers require more granular
definition of the connection between display drivers and
panels, and a proper panel compatible. This utilizes the
bindings merged to the DRM subsystem to properly define
the display on the NSPIRE devices.

We also do away with the undocumented DT binding
"lcd-type".

We add both the clocks to the CLCD block so the driver
have full control over its clocking.

Link: https://lore.kernel.org/r/20190810074230.6492-1-linus.walleij@linaro.org
Cc: Daniel Tang <dt.tangr@gmail.com>
Cc: Fabian Vogt <fabian@ritter-vogt.de>
Tested-by: Fabian Vogt <fabian@ritter-vogt.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Linus Walleij 2019-08-10 09:42:30 +02:00 committed by Arnd Bergmann
parent c08b598410
commit da5fbcb1d0
3 changed files with 36 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/boot/dts/nspire-classic.dtsi
View File

@ -8,7 +8,11 @@
/include/ "nspire.dtsi"
&lcd {
lcd-type = "classic";
port {
clcd_pads: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&fast_timer {
@ -69,6 +73,15 @@
#interrupt-cells = <1>;
};
};
panel {
compatible = "ti,nspire-classic-lcd-panel";
port {
panel_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
};
chosen {
bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
};

15
arch/arm/boot/dts/nspire-cx.dts
View File

@ -9,7 +9,11 @@
/include/ "nspire.dtsi"
&lcd {
lcd-type = "cx";
port {
clcd_pads: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&fast_timer {
@ -106,6 +110,15 @@
};
};
};
panel {
compatible = "ti,nspire-cx-lcd-panel";
port {
panel_in: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
};
chosen {
bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
};

10
arch/arm/boot/dts/nspire.dtsi
View File

@ -95,8 +95,14 @@
reg = <0xC0000000 0x1000>;
interrupts = <21>;
clocks = <&apb_pclk>;
clock-names = "apb_pclk";
/*
* We assume the same clock is fed to APB and CLCDCLK.
* There is some code to scale the clock down by a factor
* 48 for the display so likely the frequency to the
* display is 1MHz and the CLCDCLK is 48 MHz.
*/
clocks = <&apb_pclk>, <&apb_pclk>;
clock-names = "clcdclk", "apb_pclk";
};
adc: adc@C4000000 {